Remove .fdivs_offs from the fixed PLL clock trees for MT7981, MT7986,
MT7987 and MT7988. These trees have no .fdivs table, and
mtk_clk_id_is_fdiv() checks tree->fdivs before looking at the offset, so
the value is never used.
The offset used to mark where the fixed clocks ended, so it was needed
for these trees until commit d09876c4f6ac ("clk: mediatek: add
mtk_clk_id_is_* helper functions") replaced the ID range checks.
Signed-off-by: David Lechner <[email protected]>
---
Changes in v2:
- Added same change for MT7986.
- Link to v1:
https://patch.msgid.link/20261012-clk-mediatek-apmixed-fdivs-offs-v1-1-f366cc5dd...@baylibre.com
---
drivers/clk/mediatek/clk-mt7981.c | 1 -
drivers/clk/mediatek/clk-mt7986.c | 1 -
drivers/clk/mediatek/clk-mt7987.c | 1 -
drivers/clk/mediatek/clk-mt7988.c | 1 -
4 files changed, 4 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt7981.c
b/drivers/clk/mediatek/clk-mt7981.c
index 6d5c967ea78..89be561432a 100644
--- a/drivers/clk/mediatek/clk-mt7981.c
+++ b/drivers/clk/mediatek/clk-mt7981.c
@@ -619,7 +619,6 @@ static const struct mtk_gate infracfg_gates[] = {
static const struct mtk_clk_tree mt7981_fixed_pll_clk_tree = {
.ext_clk_rates = ext_clock_rates,
.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
- .fdivs_offs = CLK_APMIXED_NR_CLK,
.fclks = fixed_pll_clks,
.num_fclks = ARRAY_SIZE(fixed_pll_clks),
.type = MTK_CLK_TREE_APMIXED,
diff --git a/drivers/clk/mediatek/clk-mt7986.c
b/drivers/clk/mediatek/clk-mt7986.c
index 1e54d8ed2cf..7a806bbdfb0 100644
--- a/drivers/clk/mediatek/clk-mt7986.c
+++ b/drivers/clk/mediatek/clk-mt7986.c
@@ -526,7 +526,6 @@ static const struct mtk_gate infracfg_gates[] = {
static const struct mtk_clk_tree mt7986_fixed_pll_clk_tree = {
.ext_clk_rates = ext_clock_rates,
.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
- .fdivs_offs = CLK_APMIXED_NR_CLK,
.fclks = fixed_pll_clks,
.num_fclks = ARRAY_SIZE(fixed_pll_clks),
.flags = CLK_PARENT_APMIXED,
diff --git a/drivers/clk/mediatek/clk-mt7987.c
b/drivers/clk/mediatek/clk-mt7987.c
index 831fa7177a7..3cf008f420a 100644
--- a/drivers/clk/mediatek/clk-mt7987.c
+++ b/drivers/clk/mediatek/clk-mt7987.c
@@ -56,7 +56,6 @@ static const struct mtk_fixed_clk apmixedsys_mtk_plls[] = {
static const struct mtk_clk_tree mt7987_fixed_pll_clk_tree = {
.ext_clk_rates = ext_clock_rates,
.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
- .fdivs_offs = ARRAY_SIZE(apmixedsys_mtk_plls),
.fclks = apmixedsys_mtk_plls,
.num_fclks = ARRAY_SIZE(apmixedsys_mtk_plls),
.flags = CLK_PARENT_APMIXED,
diff --git a/drivers/clk/mediatek/clk-mt7988.c
b/drivers/clk/mediatek/clk-mt7988.c
index 797274c59ca..3adea0cd9e1 100644
--- a/drivers/clk/mediatek/clk-mt7988.c
+++ b/drivers/clk/mediatek/clk-mt7988.c
@@ -804,7 +804,6 @@ static const struct mtk_gate infracfg_mtk_gates[] = {
static const struct mtk_clk_tree mt7988_fixed_pll_clk_tree = {
.ext_clk_rates = ext_clock_rates,
.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
- .fdivs_offs = ARRAY_SIZE(apmixedsys_mtk_plls),
.fclks = apmixedsys_mtk_plls,
.num_fclks = ARRAY_SIZE(apmixedsys_mtk_plls),
.flags = CLK_PARENT_APMIXED,
---
base-commit: fed92546960a92177d67c0b8d7b22385f50fed29
base-tree: https://git.u-boot-project.org/u-boot/u-boot.git main
change-id: 20261012-clk-mediatek-apmixed-fdivs-offs-aca845a1bf0a
Best regards,
--
David Lechner <[email protected]>
