The CLK_PCIE30PHY_REF_M and CLK_PCIE30PHY_REF_N clocks are by default gated coming out from system reset. The probe() ops of the PMUCRU driver unconditionally ungate these clocks to help ensure PCIe works in U-Boot proper.
Change to only ungate these clocks when the PCI Kconfig option is enabled for current boot phase to delay the ungate as late as possible. Signed-off-by: Jonas Karlman <[email protected]> --- Changes in v3: - New optional patch to help delay the ungate of PCIe ref clocks until U-Boot proper This patch is strictly not needed, however it seems very unnecessary to ungate PCIe ref clocks in SPL when PCIe typically only is used in proper. Ideally this should be moved to enable()/disable() ops, however that would also require working implementation of enable_count for these clocks as they can be shared between both PCIe controllers. Something that can be deferred to a planned future clock driver refactor series. --- drivers/clk/rockchip/clk_rk3568.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c index 9f3e9322161e..ce17d42ea0f0 100644 --- a/drivers/clk/rockchip/clk_rk3568.c +++ b/drivers/clk/rockchip/clk_rk3568.c @@ -477,7 +477,9 @@ static int rk3568_pmuclk_probe(struct udevice *dev) } /* Ungate PCIe30phy refclk_m and refclk_n */ - rk_clrsetreg(&priv->pmucru->pmu_clkgate_con[2], 0x3 << 13, 0 << 13); + if (CONFIG_IS_ENABLED(PCI)) + rk_clrreg(&priv->pmucru->pmu_clkgate_con[2], 0x3 << 13); + return 0; } -- 2.55.0
