Hi Kuan-Wei,
On 2026-10-16T04:02:12, Kuan-Wei Chiu <[email protected]> wrote:
> board: google: Add Google Tensor G5 board support
>
> Add initial board support for Google Tensor G5 SoC boards. U-Boot
> runs as BL33 loaded at 0xbe000000. Configure the MMU map, DRAM
> bounds, and disable the APC watchdog left running by earlier
> bootloader stages.
>
> Signed-off-by: Kuan-Wei Chiu <[email protected]>
>
> MAINTAINERS | 2 ++
> arch/arm/mach-google/Kconfig | 11 ++++++++
> board/google/lga/Kconfig | 14 ++++++++++
> board/google/lga/MAINTAINERS | 5 ++++
> board/google/lga/Makefile | 3 ++
> board/google/lga/lga.c | 65
> ++++++++++++++++++++++++++++++++++++++++++++
> include/configs/lga.h | 9 ++++++
> 7 files changed, 109 insertions(+)
> U-Boot 2026.10-00821-g86c1a8698ac2 (Oct 14 2026 - 21:47:47 +0000)
>
> Model: Frankel
> DRAM: 2 GiB
> ERROR: reserving fdt memory region failed (addr=be000000 size=1000000
> flags=2): -17
Just to check, is this -EEXIST because the DT already carries a
reserved-memory entry covering the BL33 load region, or something
U-Boot adds itself twice ? Worth tracking down before the series lands
rather than leaving a visible ERROR on every boot.
> diff --git a/board/google/lga/lga.c b/board/google/lga/lga.c
> @@ -0,0 +1,65 @@
> +#define LGA_SDRAM_BASE 0x80000000UL
> +#define LGA_SDRAM_SIZE 0x80000000UL
> +#define LGA_BL33_RAM_TOP 0xc0000000UL
The Kconfig help text lists Frankel, Blazer and Mustang, which ship
with different DRAM sizes (Pixel 10 Pro / Pro XL have well over 2
GiB). Hard-coding 2 GiB means those variants will only ever see the
first bank and the mem_map will not cover the rest. Please can you
pick the base/size up from the device tree
(fdtdec_setup_mem_size_base() or similar) so the same board directory
works for all three.
> diff --git a/board/google/lga/lga.c b/board/google/lga/lga.c
> @@ -0,0 +1,65 @@
> +int board_init(void)
> +{
> + writel(LGA_WDT_KEY_UNLOCK, LGA_WDT1_BASE + LGA_WDT_KEY);
> + clrbits_le32(LGA_WDT1_BASE + LGA_WDT_CONTROL, LGA_WDT_CONTROL_ENABLE);
> + writel(0, LGA_WDT1_BASE + LGA_WDT_KEY);
> +
> + return 0;
> +}
The APC watchdog is a SoC-level block, so this would sit more
naturally under arch/arm/mach-google/ and be shared by any future lga
board. What do you think?
Regards,
Simon
