sha256_armv8_ce_process() loads and stores the hash state with
ldp dga, dgb, [x0]
stp dga, dgb, [x0]
This requires the address to be 16-byte aligned when alignment is
enforced, e.g. when running with the MMU disabled as in SPL, where all
data accesses are treated as Device memory.
The state pointer sha256_context.state is located at offset 8 within
the context, after total[2]. Depending on where the context ends up on
the stack, the state is therefore only 8-byte aligned leading to an
alignment fault (ESR 0x96000021).
Use ld1/st1 with the vector views of the same registers instead, as
the Linux implementation does.
Fixes: 0fcc1c76d1ac ("armv8 SHA-256 using ARMv8 Crypto Extensions")
Signed-off-by: Tycho Kirchner <[email protected]>
---
arch/arm/cpu/armv8/sha256_ce_core.S | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv8/sha256_ce_core.S
b/arch/arm/cpu/armv8/sha256_ce_core.S
index fbae3ca362b..ea918dfc35b 100644
--- a/arch/arm/cpu/armv8/sha256_ce_core.S
+++ b/arch/arm/cpu/armv8/sha256_ce_core.S
@@ -85,7 +85,7 @@ ENTRY(sha256_armv8_ce_process)
ld1 {v12.4s-v15.4s}, [x8]
/* load state */
- ldp dga, dgb, [x0]
+ ld1 {dgav.4s, dgbv.4s}, [x0]
/* load input */
0: ld1 {v16.4s-v19.4s}, [x1], #64
@@ -129,6 +129,6 @@ ENTRY(sha256_armv8_ce_process)
cbnz w2, 0b
/* store new state */
-3: stp dga, dgb, [x0]
+3: st1 {dgav.4s, dgbv.4s}, [x0]
ret
ENDPROC(sha256_armv8_ce_process)
--
2.47.3
