[PATCH v2 4/7] clk: rockchip: rk3576: Remove unnecessary clk_set_defaults() call

[Jonas Karlman]

Commit fd1ba2965244 ("drivers: clk: Fix using assigned-clocks in the
node of the clock it sets up"), first included in v2020.01-rc2, added
a clock-uclass post_probe() hook that applies clock controllers own
assigned clocks.

Remove the redundant clk_set_defaults() call from the RK3576 clock
driver probe() ops. Also remove the unused sync_kernel field that only
recorded whether assigned clocks had been applied.

Fixes: 3919310b37ec ("clk: rockchip: Add rk3576 clk support")
Signed-off-by: Jonas Karlman <jo...@kwiboo.se>
---
v2: Remove the unchecked ret variable
---
 arch/arm/include/asm/arch-rockchip/cru_rk3576.h |  1 -
 drivers/clk/rockchip/clk_rk3576.c               | 14 ++------------
 2 files changed, 2 insertions(+), 13 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3576.h 
b/arch/arm/include/asm/arch-rockchip/cru_rk3576.h
index 41e225245843..c9a4b1a47b6f 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3576.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3576.h
@@ -46,7 +46,6 @@ struct rk3576_clk_priv {
        ulong armclk_hz;
        ulong armclk_enter_hz;
        ulong armclk_init_hz;
-       bool sync_kernel;
        bool set_armclk_rate;
 };
 
diff --git a/drivers/clk/rockchip/clk_rk3576.c 
b/drivers/clk/rockchip/clk_rk3576.c
index 1988f0472dec..1a2ac14b63a5 100644
--- a/drivers/clk/rockchip/clk_rk3576.c
+++ b/drivers/clk/rockchip/clk_rk3576.c
@@ -2443,9 +2443,6 @@ static void rk3576_clk_init(struct rk3576_clk_priv *priv)
 static int rk3576_clk_probe(struct udevice *dev)
 {
        struct rk3576_clk_priv *priv = dev_get_priv(dev);
-       int ret;
-
-       priv->sync_kernel = false;
 
 #ifdef CONFIG_SPL_BUILD
        /* relase presetn_bigcore_biu/cru/grf */
@@ -2471,8 +2468,8 @@ static int rk3576_clk_probe(struct udevice *dev)
        rockchip_pll_set_rate(&rk3576_pll_clks[BPLL], priv->cru,
                              BPLL, LPLL_HZ);
        if (!priv->armclk_enter_hz) {
-               ret = rockchip_pll_set_rate(&rk3576_pll_clks[LPLL], priv->cru,
-                                           LPLL, LPLL_HZ);
+               rockchip_pll_set_rate(&rk3576_pll_clks[LPLL], priv->cru,
+                                     LPLL, LPLL_HZ);
                priv->armclk_enter_hz =
                        rockchip_pll_get_rate(&rk3576_pll_clks[LPLL],
                                              priv->cru, LPLL);
@@ -2501,13 +2498,6 @@ static int rk3576_clk_probe(struct udevice *dev)
 
        rk3576_clk_init(priv);
 
-       /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
-       ret = clk_set_defaults(dev, 1);
-       if (ret)
-               debug("%s clk_set_defaults failed %d\n", __func__, ret);
-       else
-               priv->sync_kernel = true;
-
        return 0;
 }
 
-- 
2.56.0