This series fixes and improves the Cadence QSPI/OSPI driver for the AMD Versal and Versal NET platforms.
Indirect write handling: - Poll the Indirect Operation Complete bit in the IRQ status register instead of waiting for the SRAM fill level to drain, and increase the indirect write timeouts to 500 ms as in the Linux driver. This fixes indirect write timeouts on Versal and Versal NET. - Write a 4-byte aligned word to ahbbase for the unaligned tail of a transfer, avoiding AHB bus errors. Controller initialization: - Clear stale controller register contents left over from a previous boot stage after a soft reset. - Initialize the read and write watermark registers (1/2 and 1/8 of the FIFO, as in the Linux driver). - Set the tap granularity selection bit in the ECO register on Versal for reference clocks of 120 MHz and above, which octal SPI needs to work properly. DMA and reads: - Enable the DMA DONE interrupt and wait for the DMA BUSY bit to clear before accepting a new command. - Stop overwriting the dummy cycles in RD_INSTR with a hardcoded value for partial reads on Versal, which caused data mismatches. Padmarao Begari (7): spi: cadence_qspi: Fix indirect write timeout spi: cadence_qspi: Clean up registers in init spi: cadence_qspi: Initialize read and write watermark registers spi: cadence_qspi: Enable ECO bit for higher frequencies spi: cadence_qspi: Write aligned byte length to ahbbase spi: cadence_ospi_versal: Enable the DMA DONE interrupt spi: cadence_ospi_versal: Remove explicit dummy cycle setting drivers/spi/cadence_ospi_versal.c | 24 +++++++-- drivers/spi/cadence_qspi.h | 19 +++++++ drivers/spi/cadence_qspi_apb.c | 82 ++++++++++++++++++++++++++----- 3 files changed, 110 insertions(+), 15 deletions(-) -- 2.34.1
