Hi Alastair, I checked gpio_init() in arch/arm/mach-sunxi/board.c on your A733 branch (5887f2b) and ran it on my Cubie A7Z from cold FEL, stopping right after it.
The common code copies PIO+0x348 to PIO+0x340 using the H6 power-mode offsets. On the A733 those are PF_EINT_CFG2 and PF_EINT_CFG0, while the power-mode registers are at 0x48/0x40. So the copy writes PF's interrupt configuration instead. Both EINT registers were zero in that test, so nothing changed, but the addresses are still wrong for what the code intends. The A733-specific code also clears bit 5 at PIO+0x40 to force PF to 3.3V. That bit belongs to PC's field; PF is bits 11:10. I tried clearing it after an SD boot and saw no difference on the A7Z, where the PC pins aren't connected. With my mainline setup, PF in 00, 10 and AUTO (01) all worked at 3.3V and 25 MHz. I can't test SDR104 there yet. An earlier, limited test with the vendor kernel timed out with PF fixed at 3.3V and worked in AUTO. I didn't run your full SPL, since its PMIC setup doesn't match this board. Only gpio_init() was exercised. Thanks, Vinicius
