On 2026-10-11T22:28:36, Jonas Karlman <[email protected]> wrote: > clk: rockchip: pll: Fix fractional PLL rate calculation > > The fractional part of the rk3036-style PLL rate is divided by > postdiv1 twice instead of by both postdiv1 and postdiv2. The integer > part also loses precision by calculating in MHz before converting to Hz. > > Calculate both parts in Hz using u64 arithmetic and apply post-dividers > on the combined integer and fractional parts. This also closely matches > the Linux implementation. > > Fixes: bbda2ed5840c ("rockchip: clk: pll: add common pll setting funcs") > Signed-off-by: Jonas Karlman <[email protected]> > > drivers/clk/rockchip/clk_pll.c | 11 ++++++----- > 1 file changed, 6 insertions(+), 5 deletions(-)
Reviewed-by: Simon Glass <[email protected]>
