Hi Jonas,
On 2026-10-11T22:28:36, Jonas Karlman <[email protected]> wrote:
> clk: rockchip: rk3576: Fix ACLK_TOP_MID parent selection
>
> Write the intended parent clock for the calculated divisor instead of
> forcing it to GPLL when ACLK_TOP_MID rate is changed.
>
> Fixes: 3919310b37ec ("clk: rockchip: Add rk3576 clk support")
> Signed-off-by: Jonas Karlman <[email protected]>
>
> drivers/clk/rockchip/clk_rk3576.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
> diff --git a/drivers/clk/rockchip/clk_rk3576.c
> b/drivers/clk/rockchip/clk_rk3576.c
> @@ -320,8 +320,7 @@ static ulong rk3576_top_set_clk(struct rk3576_clk_priv
> *priv,
> - (ACLK_TOP_MID_SEL_GPLL <<
> - ACLK_TOP_MID_SEL_SHIFT) |
> + (src_clk << ACLK_TOP_MID_SEL_SHIFT) |
> (src_clk_div - 1) << ACLK_TOP_MID_DIV_SHIFT);
BTW the ACLK_TOP case just above has a similar copy-paste mistake. It
shifts the divider by the select shift:
(src_clk_div - 1) << ACLK_TOP_SEL_SHIFT);
It should use ACLK_TOP_DIV_SHIFT (0). As it stands the divider lands
in bits 5 and 6 and overwrites the parent selection, while the real
divider field is cleared, so ACLK_TOP gets the wrong rate whenever it
is set. It would be worth fixing this in the series, either here or in
a separate patch.
Reviewed-by: Simon Glass <[email protected]>
