On 2026-10-11T22:28:36, Jonas Karlman <[email protected]> wrote: > clk: rockchip: rk3576: Use correct mode register for VPLL > > Change to use correct PLL mode register when VPLL rate is changed. > > Fixes: 3919310b37ec ("clk: rockchip: Add rk3576 clk support") > Signed-off-by: Jonas Karlman <[email protected]> > > drivers/clk/rockchip/clk_rk3576.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Simon Glass <[email protected]>
