On 2026-10-11T22:28:36, Jonas Karlman <[email protected]> wrote: > clk: rockchip: rk3588: Use SPLL_HZ constant > > The SPLL rate is set to SPLL_HZ (702 MHz) in SPL phase. > > Replace '702 * MHz' with use of the SPLL_HZ constant for consistency. > > Signed-off-by: Jonas Karlman <[email protected]> > Reviewed-by: Quentin Schulz <[email protected]> > > drivers/clk/rockchip/clk_rk3588.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-)
Reviewed-by: Simon Glass <[email protected]>
