The DRAM mode register 1 value belongs to the DRAM part, and the parts in use differ: 0x02 for the DDR2 die co-packaged with the D1s and F133-A, against the 0x42 that the boards with external DDR3 have booted with so far.
Expose it next to the other vendor DRAM settings, keeping 0x42 as the default so nothing changes for the existing users. Signed-off-by: Indrek Kruusa <[email protected]> --- drivers/ram/sunxi/Kconfig | 6 ++++++ drivers/ram/sunxi/dram_sun20i_d1.c | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/ram/sunxi/Kconfig b/drivers/ram/sunxi/Kconfig index 9f2dc4a6e66..9b0cbca8083 100644 --- a/drivers/ram/sunxi/Kconfig +++ b/drivers/ram/sunxi/Kconfig @@ -12,6 +12,12 @@ config DRAM_SUNXI_ODT_EN help ODT EN value from vendor DRAM settings. +config DRAM_SUNXI_MR1 + hex "DRAM MR1 parameter" + default 0x42 + help + DRAM mode register 1 value from vendor DRAM settings. + config DRAM_SUNXI_TPR0 hex "DRAM TPR0 parameter" help diff --git a/drivers/ram/sunxi/dram_sun20i_d1.c b/drivers/ram/sunxi/dram_sun20i_d1.c index 2d81e58071c..b8aef9707cc 100644 --- a/drivers/ram/sunxi/dram_sun20i_d1.c +++ b/drivers/ram/sunxi/dram_sun20i_d1.c @@ -1420,7 +1420,7 @@ static const dram_para_t para = { .dram_zq = CONFIG_DRAM_ZQ, .dram_odt_en = CONFIG_DRAM_SUNXI_ODT_EN, .dram_mr0 = 0x1c70, - .dram_mr1 = 0x42, + .dram_mr1 = CONFIG_DRAM_SUNXI_MR1, .dram_mr2 = 0x18, .dram_mr3 = 0, .dram_tpr0 = 0x004a2195, -- 2.43.0
