Due to SPL image running in a memory space constraint SRAM environment, so reduce the whole clock tree a bit to make it fit for final runtime requirement, only a subset clock tree is registered, which includes UART, SDHCI, I2C (TWSI), and their PLL/MPMU/APMU/APBC ancestors; while the full clock tree is retained in non-SPL build.
Where surviving SPL CCU definitions reference parent clocks outside that subset tree, it will use "clock-dummy" as name of clock parent to ensure the framework still successfully resolves the parent clock lookup. Signed-off-by: Yixun Lan <[email protected]> --- Changes in v2: - add gpio clock - fix tswi8 clock - enable sdh0 clock - Link to v1: https://patch.msgid.link/[email protected] --- drivers/clk/spacemit/clk-k3.c | 209 ++++++++++++++++++++++++++++++++++++++---- 1 file changed, 190 insertions(+), 19 deletions(-) diff --git a/drivers/clk/spacemit/clk-k3.c b/drivers/clk/spacemit/clk-k3.c index f4f1bb7bf04..de7d2ae0864 100644 --- a/drivers/clk/spacemit/clk-k3.c +++ b/drivers/clk/spacemit/clk-k3.c @@ -42,6 +42,18 @@ static const struct ccu_pll_rate_tbl pll1_rate_tbl[] = { CCU_PLLA_RATE(2457600000UL, 0x0b330ccc, 0x0000cd00, 0xa0558989), }; +#if IS_ENABLED(CONFIG_SPL_BUILD) +CCU_PLLA_DEFINE(CLK_PLL1, pll1, pll1, "clock-24m", pll1_rate_tbl, + APBS_PLL1_SWCR1, APBS_PLL1_SWCR2, APBS_PLL1_SWCR3, + MPMU_POSR, POSR_PLL1_LOCK, CLK_SET_RATE_GATE); +CCU_FACTOR_GATE_DEFINE(CLK_PLL1_D4, pll1_d4, pll1_d4, "pll1", + APBS_PLL1_SWCR2, BIT(3), 4, 1); +CCU_FACTOR_GATE_DEFINE(CLK_PLL1_D6, pll1_d6, pll1_d6, "pll1", + APBS_PLL1_SWCR2, BIT(5), 6, 1); +CCU_FACTOR_GATE_FLAGS_DEFINE(CLK_PLL1_D8, pll1_d8, pll1_d8, "pll1", + APBS_PLL1_SWCR2, BIT(7), 8, 1, + CLK_IS_CRITICAL); +#else static const struct ccu_pll_rate_tbl pll2_rate_tbl[] = { CCU_PLLA_RATE(3000000000UL, 0x0b3e2000, 0x00000000, 0xa0558c8c), }; @@ -337,9 +349,51 @@ CCU_FACTOR_GATE_DEFINE(CLK_PLL8_D7, pll8_d7, pll8_d7, "pll8", APBS_PLL8_SWCR2, BIT(6), 7, 1); CCU_FACTOR_GATE_DEFINE(CLK_PLL8_D8, pll8_d8, pll8_d8, "pll8", APBS_PLL8_SWCR2, BIT(7), 8, 1); +#endif /* APBS clocks end */ /* MPMU clocks start */ +#if IS_ENABLED(CONFIG_SPL_BUILD) +CCU_GATE_DEFINE(CLK_MPMU_PLL1_307P2, pll1_d8_307p2, pll1_d8_307p2, "pll1_d8", + MPMU_ACGR, BIT(13), 0); +CCU_GATE_DEFINE(CLK_MPMU_PLL1_409P6, pll1_d6_409p6, pll1_d6_409p6, "pll1_d6", + MPMU_ACGR, BIT(0), 0); +CCU_FACTOR_DEFINE(CLK_MPMU_PLL1_61P44, pll1_d40_61p44, pll1_d40_61p44, + "pll1_d8_307p2", 5, 1); +CCU_FACTOR_DEFINE(CLK_MPMU_PLL1_153P6, pll1_d16_153p6, + pll1_d16_153p6, "pll1_d8", 2, 1); +CCU_FACTOR_GATE_DEFINE(CLK_MPMU_PLL1_102P4, pll1_d24_102p4, + pll1_d24_102p4, "pll1_d8", MPMU_ACGR, + BIT(12), 3, 1); +CCU_FACTOR_GATE_DEFINE(CLK_MPMU_PLL1_51P2, pll1_d48_51p2, + pll1_d48_51p2, "pll1_d8", MPMU_ACGR, + BIT(7), 6, 1); +CCU_FACTOR_GATE_DEFINE(CLK_MPMU_PLL1_57P6, pll1_m3d128_57p6, + pll1_m3d128_57p6, "pll1_d8", MPMU_ACGR, + BIT(8), 16, 3); +CCU_FACTOR_GATE_DEFINE(CLK_MPMU_PLL1_25P6, pll1_d96_25p6, + pll1_d96_25p6, "pll1_d8", MPMU_ACGR, + BIT(4), 12, 1); +CCU_GATE_DEFINE(CLK_MPMU_PLL1_614, pll1_d4_614p4, pll1_d4_614p4, + "pll1_d4", MPMU_ACGR, BIT(15), 0); +CCU_FACTOR_GATE_DEFINE(CLK_MPMU_PLL1_31P5, pll1_d78_31p5, + pll1_d78_31p5, "pll1_d4", MPMU_ACGR, + BIT(6), 39, 2); + +static const char * const apb_parents[] = { + "pll1_d96_25p6", "pll1_d48_51p2", "pll1_d96_25p6", + "pll1_d24_102p4", +}; + +CCU_MUX_DEFINE(CLK_MPMU_APB, apb_clk, apb_clk, apb_parents, + ARRAY_SIZE(apb_parents), MPMU_APBCSCR, 0, 2, 0); +CCU_DDN_DEFINE(CLK_MPMU_SLOW_UART1, slow_uart1_14p74, + slow_uart1_14p74, "pll1_d16_153p6", MPMU_SUCCR, + CCU_DDN_MASK(16, 13), 16, CCU_DDN_MASK(0, 13), 0, 2, 0); +CCU_DDN_DEFINE(CLK_MPMU_SLOW_UART2, slow_uart2_48, slow_uart2_48, + "pll1_d4_614p4", MPMU_SUCCR_1, CCU_DDN_MASK(16, 13), 16, + CCU_DDN_MASK(0, 13), 0, 2, 0); +#else CCU_GATE_DEFINE(CLK_MPMU_PLL1_307P2, pll1_d8_307p2, pll1_d8_307p2, "pll1_d8", MPMU_ACGR, BIT(13), 0); CCU_FACTOR_DEFINE(CLK_MPMU_PLL1_76P8, pll1_d32_76p8, pll1_d32_76p8, "pll1_d8_307p2", 4, 1); @@ -476,12 +530,49 @@ CCU_GATE_DEFINE(CLK_MPMU_I2S4_SYSCLK, i2s4_sysclk, i2s4_sysclk, "i2s4_sysclk_div MPMU_I2S_SYSCLK_CTRL, BIT(18), 0); CCU_GATE_DEFINE(CLK_MPMU_I2S5_SYSCLK, i2s5_sysclk, i2s5_sysclk, "i2s5_sysclk_div", MPMU_I2S_SYSCLK_CTRL, BIT(22), 0); +#endif /* MPMU clocks end */ /* APBC clocks start */ static const char * const uart_clk_parents[] = { "pll1_m3d128_57p6", "slow_uart1_14p74", "slow_uart2_48", }; + +#if IS_ENABLED(CONFIG_SPL_BUILD) +CCU_MUX_GATE_DEFINE(CLK_APBC_UART0, uart0_clk, uart0_clk, + uart_clk_parents, ARRAY_SIZE(uart_clk_parents), + APBC_UART0_CLK_RST, 4, 3, BIT(1), 0); +CCU_GATE_DEFINE(CLK_APBC_UART0_BUS, uart0_bus_clk, uart0_bus_clk, + "apb_clk", APBC_UART0_CLK_RST, BIT(0), 0); +CCU_GATE_DEFINE(CLK_APBC_AIB, aib_clk, aib_clk, "clock-24m", + APBC_AIB_CLK_RST, BIT(1), 0); +CCU_GATE_DEFINE(CLK_APBC_AIB_BUS, aib_bus_clk, aib_bus_clk, "apb_clk", + APBC_AIB_CLK_RST, BIT(0), 0); + +static const char * const twsi_parents[] = { + "pll1_d78_31p5", +}; + +CCU_MUX_GATE_DEFINE(CLK_APBC_TWSI2, twsi2_clk, twsi2_clk, + twsi_parents, ARRAY_SIZE(twsi_parents), + APBC_TWSI2_CLK_RST, 4, 3, BIT(1), 0); +CCU_GATE_DEFINE(CLK_APBC_TWSI2_BUS, twsi2_bus_clk, twsi2_bus_clk, + "apb_clk", APBC_TWSI2_CLK_RST, BIT(0), 0); +CCU_GATE_DEFINE(CLK_APBC_GPIO, gpio_clk, gpio_clk, "clock-24m", + APBC_GPIO_CLK_RST, BIT(1), 0); +CCU_GATE_DEFINE(CLK_APBC_GPIO_BUS, gpio_bus_clk, gpio_bus_clk, "apb_clk", + APBC_GPIO_CLK_RST, BIT(0), 0); + +static const char * const twsi8_parents[] = { + "pll1_d78_31p5", "pll1_d48_51p2", "pll1_d40_61p44", +}; + +CCU_MUX_GATE_DEFINE(CLK_APBC_TWSI8, twsi8_clk, twsi8_clk, + twsi8_parents, ARRAY_SIZE(twsi8_parents), + APBC_TWSI8_CLK_RST, 4, 3, BIT(1), 0); +CCU_GATE_DEFINE(CLK_APBC_TWSI8_BUS, twsi8_bus_clk, twsi8_bus_clk, "apb_clk", + APBC_TWSI8_CLK_RST, BIT(0), 0); +#else CCU_MUX_GATE_DEFINE(CLK_APBC_UART0, uart0_clk, uart0_clk, uart_clk_parents, ARRAY_SIZE(uart_clk_parents), APBC_UART0_CLK_RST, 4, 3, BIT(1), 0); CCU_MUX_GATE_DEFINE(CLK_APBC_UART2, uart2_clk, uart2_clk, uart_clk_parents, ARRAY_SIZE(uart_clk_parents), @@ -843,9 +934,31 @@ CCU_GATE_DEFINE(CLK_APBC_CAN3_BUS, can3_bus_clk, can3_bus_clk, "apb_clk", APBC_CAN3_CLK_RST, BIT(0), 0); CCU_GATE_DEFINE(CLK_APBC_CAN4_BUS, can4_bus_clk, can4_bus_clk, "apb_clk", APBC_CAN4_CLK_RST, BIT(0), 0); +#endif /* APBC clocks end */ /* APMU clocks start */ +#if IS_ENABLED(CONFIG_SPL_BUILD) +static const char * const axi_clk_parents[] = { + "pll1_d8_307p2", "pll1_d6_409p6", +}; + +CCU_MUX_DIV_FC_DEFINE(CLK_APMU_AXICLK, axi_clk, axi_clk, + axi_clk_parents, ARRAY_SIZE(axi_clk_parents), + APMU_ACLK_CLK_CTRL, APMU_ACLK_CLK_CTRL, 1, 2, + BIT(4), 0, 1, 0); +CCU_GATE_DEFINE(CLK_APMU_SDH_AXI, sdh_axi_aclk, sdh_axi_aclk, "axi_clk", + APMU_SDH0_CLK_RES_CTRL, BIT(3), 0); + +static const char * const sdh01_parents[] = { + "pll1_d6_409p6", +}; + +CCU_MUX_DIV_GATE_FC_DEFINE(CLK_APMU_SDH0, sdh0_clk, sdh0_clk, + sdh01_parents, ARRAY_SIZE(sdh01_parents), + APMU_SDH0_CLK_RES_CTRL, 8, 3, BIT(11), + 5, 3, BIT(4), 0); +#else static const char * const axi_clk_parents[] = { "pll1_d8_307p2", "pll1_d6_409p6", }; @@ -1122,13 +1235,13 @@ CCU_MUX_DIV_GATE_FC_DEFINE(CLK_APMU_UFS_ACLK, ufs_aclk, ufs_aclk, ufs_aclk_paren 2, 3, BIT(1), 0); static const char * const edp0_pclk_parents[] = { - "lcd_pxclk", "external_clk", + "lcd_pxclk", "clock-dummy", }; CCU_MUX_GATE_DEFINE(CLK_APMU_EDP0_PXCLK, edp0_pxclk, edp0_pxclk, edp0_pclk_parents, ARRAY_SIZE(edp0_pclk_parents), APMU_LCD_EDP_CTRL, 2, 1, BIT(1), 0); static const char * const edp1_pclk_parents[] = { - "dsi4ln2_lcd_pxclk", "external_clk", + "dsi4ln2_lcd_pxclk", "clock-dummy", }; CCU_MUX_GATE_DEFINE(CLK_APMU_EDP1_PXCLK, edp1_pxclk, edp1_pxclk, edp1_pclk_parents, ARRAY_SIZE(edp1_pclk_parents), APMU_LCD_EDP_CTRL, 18, 1, BIT(17), 0); @@ -1189,7 +1302,7 @@ CCU_MUX_DEFINE(CLK_APMU_ESPI_SCLK_SRC, espi_sclk_src, espi_sclk_src, espi_sclk_s APMU_ESPI_CLK_RES_CTRL, 4, 3, 0); static const char * const espi_sclk_parents[] = { - "external_clk", "espi_sclk_src", + "clock-dummy", "espi_sclk_src", }; CCU_MUX_GATE_DEFINE(CLK_APMU_ESPI_SCLK, espi_sclk, espi_sclk, espi_sclk_parents, ARRAY_SIZE(espi_sclk_parents), APMU_ESPI_CLK_RES_CTRL, 7, 1, BIT(3), 0); @@ -1217,8 +1330,10 @@ CCU_MUX_DIV_GATE_DEFINE(CLK_APMU_ISIM_VCLK2, isim_vclk_out2, isim_vclk_out2, isi CCU_MUX_DIV_GATE_DEFINE(CLK_APMU_ISIM_VCLK3, isim_vclk_out3, isim_vclk_out3, isim_vclk_parents, ARRAY_SIZE(isim_vclk_parents), APMU_SNR_ISIM_VCLK_CTRL, 27, 4, 25, 2, BIT(24), 0); +#endif /* APMU clocks end */ +#if !IS_ENABLED(CONFIG_SPL_BUILD) /* DCIU clocks start */ CCU_GATE_DEFINE(CLK_DCIU_HDMA, hdma_clk, hdma_clk, "axi_clk", DCIU_DMASYS_CLK_EN, BIT(0), 0); @@ -1229,18 +1344,16 @@ CCU_GATE_DEFINE(CLK_DCIU_C2_TCM_PIPE, c2_tcm_pipe_clk, c2_tcm_pipe_clk, "axi_clk CCU_GATE_DEFINE(CLK_DCIU_C3_TCM_PIPE, c3_tcm_pipe_clk, c3_tcm_pipe_clk, "axi_clk", DCIU_C3_TCM_PIPE_CLK, BIT(0), 0); /* DCIU clocks end */ +#endif - - - - - - - - - - - +#if IS_ENABLED(CONFIG_SPL_BUILD) +static struct clk *k3_ccu_pll_clks[] = { + &pll1.common.clk, + &pll1_d4.common.clk, + &pll1_d6.common.clk, + &pll1_d8.common.clk, +}; +#else static struct clk *k3_ccu_pll_clks[] = { &pll1.common.clk, &pll2.common.clk, @@ -1328,6 +1441,7 @@ static struct clk *k3_ccu_pll_clks[] = { &pll8_d7.common.clk, &pll8_d8.common.clk, }; +#endif static const struct spacemit_ccu_data k3_ccu_pll_data = { .clks = k3_ccu_pll_clks, @@ -1335,6 +1449,23 @@ static const struct spacemit_ccu_data k3_ccu_pll_data = { .offset = K3_PLL_ID, }; +#if IS_ENABLED(CONFIG_SPL_BUILD) +static struct clk *k3_ccu_mpmu_clks[] = { + &pll1_d8_307p2.common.clk, + &pll1_d6_409p6.common.clk, + &pll1_d40_61p44.common.clk, + &pll1_d16_153p6.common.clk, + &pll1_d24_102p4.common.clk, + &pll1_d48_51p2.common.clk, + &pll1_m3d128_57p6.common.clk, + &pll1_d96_25p6.common.clk, + &pll1_d4_614p4.common.clk, + &pll1_d78_31p5.common.clk, + &apb_clk.common.clk, + &slow_uart1_14p74.common.clk, + &slow_uart2_48.common.clk, +}; +#else static struct clk *k3_ccu_mpmu_clks[] = { &pll1_d8_307p2.common.clk, &pll1_d32_76p8.common.clk, @@ -1388,6 +1519,7 @@ static struct clk *k3_ccu_mpmu_clks[] = { &i2s4_sysclk.common.clk, &i2s5_sysclk.common.clk, }; +#endif static const struct spacemit_ccu_data k3_ccu_mpmu_data = { .clks = k3_ccu_mpmu_clks, @@ -1395,6 +1527,20 @@ static const struct spacemit_ccu_data k3_ccu_mpmu_data = { .offset = K3_MPMU_ID, }; +#if IS_ENABLED(CONFIG_SPL_BUILD) +static struct clk *k3_ccu_apbc_clks[] = { + &uart0_clk.common.clk, + &uart0_bus_clk.common.clk, + &aib_clk.common.clk, + &aib_bus_clk.common.clk, + &gpio_clk.common.clk, + &gpio_bus_clk.common.clk, + &twsi2_clk.common.clk, + &twsi2_bus_clk.common.clk, + &twsi8_clk.common.clk, + &twsi8_bus_clk.common.clk, +}; +#else static struct clk *k3_ccu_apbc_clks[] = { &uart0_clk.common.clk, &uart2_clk.common.clk, @@ -1539,6 +1685,7 @@ static struct clk *k3_ccu_apbc_clks[] = { &can3_bus_clk.common.clk, &can4_bus_clk.common.clk, }; +#endif static const struct spacemit_ccu_data k3_ccu_apbc_data = { .clks = k3_ccu_apbc_clks, @@ -1546,6 +1693,13 @@ static const struct spacemit_ccu_data k3_ccu_apbc_data = { .offset = K3_APBC_ID, }; +#if IS_ENABLED(CONFIG_SPL_BUILD) +static struct clk *k3_ccu_apmu_clks[] = { + &axi_clk.common.clk, + &sdh_axi_aclk.common.clk, + &sdh0_clk.common.clk, +}; +#else static struct clk *k3_ccu_apmu_clks[] = { &axi_clk.common.clk, &cci550_clk.common.clk, @@ -1637,6 +1791,7 @@ static struct clk *k3_ccu_apmu_clks[] = { &isim_vclk_out2.common.clk, &isim_vclk_out3.common.clk, }; +#endif static const struct spacemit_ccu_data k3_ccu_apmu_data = { .clks = k3_ccu_apmu_clks, @@ -1650,13 +1805,16 @@ static const struct spacemit_ccu_data k3_ccu_apmu_data = { * Enable them explicitly here, otherwise Linux gets stuck * halfway through boot. */ +#if !IS_ENABLED(CONFIG_SPL_BUILD) static struct clk *const k3_apmu_boot_clks[] = { &cpu_c0_core_clk.common.clk, &cpu_c1_core_clk.common.clk, &cpu_c2_core_clk.common.clk, &cpu_c3_core_clk.common.clk, }; +#endif +#if !IS_ENABLED(CONFIG_SPL_BUILD) static struct clk *k3_ccu_dciu_clks[] = { &hdma_clk.common.clk, &dma350_clk.common.clk, @@ -1669,6 +1827,7 @@ static const struct spacemit_ccu_data k3_ccu_dciu_data = { .num = ARRAY_SIZE(k3_ccu_dciu_clks), .offset = K3_DCIU_ID, }; +#endif static int k3_clk_force_probe(const struct driver *drv) { @@ -1768,7 +1927,7 @@ static int k3_apmu_clk_probe(struct udevice *dev) { struct regmap *base_regmap; const struct spacemit_ccu_data *data; - int i, ret; + int ret; ret = k3_clk_force_probe(DM_DRIVER_GET(k3_pll_clk)); if (ret) @@ -1787,11 +1946,13 @@ static int k3_apmu_clk_probe(struct udevice *dev) if (ret) return -EPROBE_DEFER; - for (i = 0; i < ARRAY_SIZE(k3_apmu_boot_clks); i++) { +#if !IS_ENABLED(CONFIG_SPL_BUILD) + for (int i = 0; i < ARRAY_SIZE(k3_apmu_boot_clks); i++) { ret = clk_enable(k3_apmu_boot_clks[i]); if (ret) return ret; } +#endif return 0; } @@ -1808,9 +1969,11 @@ static int k3_apbc_clk_probe(struct udevice *dev) ret = k3_clk_force_probe(DM_DRIVER_GET(k3_mpmu_clk)); if (ret) return ret; - ret = k3_clk_force_probe(DM_DRIVER_GET(k3_apmu_clk)); - if (ret) - return ret; + if (!IS_ENABLED(CONFIG_SPL_BUILD)) { + ret = k3_clk_force_probe(DM_DRIVER_GET(k3_apmu_clk)); + if (ret) + return ret; + } ret = regmap_init_mem(dev_ofnode(dev), &base_regmap); if (ret) @@ -1825,6 +1988,7 @@ static int k3_apbc_clk_probe(struct udevice *dev) return 0; } +#if !IS_ENABLED(CONFIG_SPL_BUILD) static int k3_dciu_clk_probe(struct udevice *dev) { struct regmap *base_regmap; @@ -1853,6 +2017,7 @@ static int k3_dciu_clk_probe(struct udevice *dev) return 0; } +#endif static int k3_pll_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args) { @@ -1914,6 +2079,7 @@ static int k3_apmu_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *arg return 0; } +#if !IS_ENABLED(CONFIG_SPL_BUILD) static int k3_dciu_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args) { if (args->args_count > 1) { @@ -1928,6 +2094,7 @@ static int k3_dciu_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *arg return 0; } +#endif #define K3_CLK_OPS(name) \ static const struct clk_ops k3_##name##_clk_ops = { \ @@ -1971,10 +2138,12 @@ static int k3_apmu_clk_bind(struct udevice *dev) return spacemit_k3_reset_bind(dev, SPACEMIT_K3_RESET_APMU); } +#if !IS_ENABLED(CONFIG_SPL_BUILD) static int k3_dciu_clk_bind(struct udevice *dev) { return spacemit_k3_reset_bind(dev, SPACEMIT_K3_RESET_DCIU); } +#endif static const struct udevice_id k3_mpmu_clk_match[] = { { .compatible = "spacemit,k3-syscon-mpmu", @@ -2030,6 +2199,7 @@ U_BOOT_DRIVER(k3_apmu_clk) = { .flags = DM_FLAG_PRE_RELOC, }; +#if !IS_ENABLED(CONFIG_SPL_BUILD) static const struct udevice_id k3_dciu_clk_match[] = { { .compatible = "spacemit,k3-syscon-dciu", .data = (ulong)&k3_ccu_dciu_data }, @@ -2047,3 +2217,4 @@ U_BOOT_DRIVER(k3_dciu_clk) = { .ops = &k3_dciu_clk_ops, .flags = DM_FLAG_PRE_RELOC, }; +#endif --- base-commit: ab4dc5aacf957835c295b59ef2dd28281839cb20 change-id: 20261103-01-k3-clock-spl-support-cba30ffecffa Best regards, -- Yixun Lan <[email protected]>
