Hi Erwin,
I think you are referring to the "dummy" byte at the beginning of every
spi command which ensures the 8 clock cycles between all commands. I am
not sure about the deactivated chip select, this is getting sent with an
active chip select as part of the spi_message.
union mmc_spi_command {
u8 buf[7];
struct {
u8 dummy; <-- Here
u8 code;
u8 addr1;
u8 addr2;
u8 addr3;
u8 addr4;
u8 crc;
} command;
};
Mike Lavender
Erwin Authried wrote:
Hello Steve,
does your driver take care about sending 8 clock cycles with deasserted
CS at the end of a transaction so that DO is tristated? I think that the
2.6 spi subsystem doesn't support sending clocks with deactivated
chipselect.
Regards,
Erwin
Am Freitag, den 18.05.2007, 14:24 +1000 schrieb Steve Bennett:
Hi Greg,
Likewise, a cleaned up version of the spi mmc patch.
BTW You can ditch the MCF IPS driver patch I sent. I'll send a new
version
based on mmap at some point.
Cheers,
Steve
_______________________________________________
uClinux-dev mailing list
uClinux-dev@uclinux.org
http://mailman.uclinux.org/mailman/listinfo/uclinux-dev
This message was resent by uclinux-dev@uclinux.org
To unsubscribe see:
http://mailman.uclinux.org/mailman/options/uclinux-dev
_______________________________________________
uClinux-dev mailing list
uClinux-dev@uclinux.org
http://mailman.uclinux.org/mailman/listinfo/uclinux-dev
This message was resent by uclinux-dev@uclinux.org
To unsubscribe see:
http://mailman.uclinux.org/mailman/options/uclinux-dev
