Hi David,
David Wu wrote:
On Tue, 03 Mar 2009 16:20:10 -0500, Gavin Lambert
<gav...@compacsort.com> wrote:
Quoth David Wu:
CACHE_ENABLE is defined to "nop" if CONFIG_UCBOOTLOADER is defined.
The cache setting is defined in the
bootloader in this case.
Also I would like to point out that at least the cache setting is not
quite correct if RAM size is not
16M for CONFIG_M527x.
The settings made by the CACHE_ENABLE macro are overridden fairly
quickly by the code in cacheflush.h anyway, so it might be moot :)
Those are for invalidate cache, right?
for example bellow:
#if defined(CONFIG_M527x) || defined(CONFIG_M528x)
__asm__ __volatile__ (
"movel #0x81000200, %%d0\n\t"
"movec %%d0, %%CACR\n\t"
"nop\n\t"
: : : "d0" );
#endif /* CONFIG_M527x || CONFIG_M528x */
#0x81000200 is for invalidate cache. Also ARC0 and ACR1 registers are
not modified in cacheflush.h.
But it also re-writes all the other control bits in that register.
Which is fine if they correspond exactly with what you initially
set. But will break you if you use something different.
It doesn't make any sense in my mind to not set an initial value
for this (in the kernel proper), but then expect the flush code
"to get it right".
Better would be to actually have proper configuration options for
enabling instruction and/or data cache. And to work out the proper
CACR value (using the calculated value as required for initial
setup, and when invalidating/flushing caches).
Regards
Greg
------------------------------------------------------------------------
Greg Ungerer -- Principal Engineer EMAIL: g...@snapgear.com
SnapGear, a McAfee Company PHONE: +61 7 3435 2888
825 Stanley St, FAX: +61 7 3891 3630
Woolloongabba, QLD, 4102, Australia WEB: http://www.SnapGear.com
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