However, since you have an FPGA, load-locked/store-conditional atomic sequences are probably easy instructions to add _if_ you have only one CPU. You'd just implement a store-guard flag which is cleared whenever an interrupt or trap occurs - trivial :-)
This is possible with CPUs like Mico32.
The NIOS is a propriety (and hand-optimized for their FPGA Arch) design by Altera. So you can't modify the CPU itself. You _can_ add user instructions, but same can't use special CPU registers (like interrupt enable) and can't use the CPU's memory interface (and cache), but need to implement their own memory interface to the Avalon bus. :(
-Michael _______________________________________________ uClinux-dev mailing list uClinux-dev@uclinux.org http://mailman.uclinux.org/mailman/listinfo/uclinux-dev This message was resent by uclinux-dev@uclinux.org To unsubscribe see: http://mailman.uclinux.org/mailman/options/uclinux-dev
