Hi Philippe,
On 30/08/10 20:42, Philippe De Muyter wrote:
Hi Greg,
On Mon, Aug 30, 2010 at 11:52:33AM +1000, Greg Ungerer wrote:
-static u8 intc_intpri = 0x36;
+static u8 intc_intpri = 066;
^^^
Why change this to octal?
Because it reflects the organisation of the ICRn registers :
2 bits unused
3 bits for level
3 bits for priority in level
Do you want me to add a comment ?
I think we should leave it the way it was :-)
Irrespective of encoding most headers use hex to define bit fields.
Grepping through arch/m68k/include/asm the only exception to this
is termbits.h - and that is completely historical.
Let's use symbolic constants then (apply on top of preceding patch) :
Defines look good. Probably no point having a separate header
file for these, given the only use is in intc-2.c. I would
suggest putting them directly in intc-2.c
Regards
Greg
---
Introduce new mcfintc-2.h file and use it in intc-2.c.
Signed-off-by: Philippe De Muyter<p...@macqel.be>
---
arch/m68k/include/asm/mcfintc-2.h | 47 +++++++++++++++++++++++++++++
arch/m68knommu/platform/coldfire/intc-2.c | 3 +-
2 files changed, 49 insertions(+), 1 deletions(-)
create mode 100644 arch/m68k/include/asm/mcfintc-2.h
diff --git a/arch/m68k/include/asm/mcfintc-2.h
b/arch/m68k/include/asm/mcfintc-2.h
new file mode 100644
index 0000000..ea5fd4f
--- /dev/null
+++ b/arch/m68k/include/asm/mcfintc-2.h
@@ -0,0 +1,47 @@
+/****************************************************************************/
+
+/*
+ * mcfintc-2.h -- support definitions for the 63 interrupt sources
+ * ColdFire Interrupt Controller
+ *
+ * (C) Copyright 2010, Philippe De Muyter<p...@macqel.be>
+ */
+
+/****************************************************************************/
+#ifndef mcfintc_2_h
+#define mcfintc_2_h
+/****************************************************************************/
+
+/*
+ * Definitions for the many ColdFire cores that use interrupt controllers
+ * with 63 interrupt sources, organized as 56 fully-programmable + 7
+ * fixed-level interrupt sources. This includes the 523x family,
+ * the 5270, 5271, 5274, 5275, and the 528x, 547x and 548x families.
+ */
+
+/*
+ * Bit definitions for the ICR family of registers.
+ */
+#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */
+#define MCFSIM_ICR_LEVEL1 0x08 /* Level 1 intr */
+#define MCFSIM_ICR_LEVEL2 0x10 /* Level 2 intr */
+#define MCFSIM_ICR_LEVEL3 0x18 /* Level 3 intr */
+#define MCFSIM_ICR_LEVEL4 0x20 /* Level 4 intr */
+#define MCFSIM_ICR_LEVEL5 0x28 /* Level 5 intr */
+#define MCFSIM_ICR_LEVEL6 0x30 /* Level 6 intr */
+#define MCFSIM_ICR_LEVEL7 0x38 /* Level 7 intr */
+#define MCFSIM_ICR_LEVEL(l) ((l)<<3) /* Level l intr */
+
+#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */
+#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */
+#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */
+#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
+#define MCFSIM_ICR_PRI4 0x04 /* Priority 4 intr */
+#define MCFSIM_ICR_PRI5 0x05 /* Priority 5 intr */
+#define MCFSIM_ICR_PRI6 0x06 /* Priority 6 intr */
+#define MCFSIM_ICR_PRI7 0x07 /* Priority 7 intr */
+#define MCFSIM_ICR_PRI(p) (p) /* Priority p intr */
+
+/****************************************************************************/
+#endif /* mcfintc_2_h */
diff --git a/arch/m68knommu/platform/coldfire/intc-2.c
b/arch/m68knommu/platform/coldfire/intc-2.c
index 060ff7b..c7b69fa 100644
--- a/arch/m68knommu/platform/coldfire/intc-2.c
+++ b/arch/m68knommu/platform/coldfire/intc-2.c
@@ -22,6 +22,7 @@
#include<linux/io.h>
#include<asm/coldfire.h>
#include<asm/mcfsim.h>
+#include<asm/intc-2.h>
#include<asm/traps.h>
/*
@@ -29,7 +30,7 @@
* We don't really care so much what they are, we don't rely on the
* tranditional priority interrupt scheme of the m68k/ColdFire.
*/
-static u8 intc_intpri = 066;
+static u8 intc_intpri = MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI6;
#ifdef MCFICM_INTC1
#define NR_VECS 128
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