Hi Philippe,
On 05/11/10 19:01, Philippe De Muyter wrote:
From MCF5407 ColdFire User’s Manual :
[bits 7-0] must be cleared; otherwise, performance may be affected.
Indeed, good catch.
Signed-off-by: Philippe De Muyter<p...@macqel.be>
---
arch/m68k/include/asm/m54xxacr.h | 9 ++++++++-
1 files changed, 8 insertions(+), 1 deletions(-)
diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h
index 27cd530..259fa8d 100644
--- a/arch/m68k/include/asm/m54xxacr.h
+++ b/arch/m68k/include/asm/m54xxacr.h
@@ -26,7 +26,7 @@
#define CACR_IHLCK 0x00000800 /* Intruction cache half lock */
#define CACR_IDCM 0x00000400 /* Intruction cache inhibit */
#define CACR_ICINVA 0x00000100 /* Invalidate instr cache */
-#define CACR_EUSP 0x00000020 /* Enable separate user a7 */
+#define CACR_EUSP 0x00000020 /* Enable separate user a7 */
#define ACR_BASE_POS 24 /* Address Base */
#define ACR_MASK_POS 16 /* Address Mask */
@@ -45,6 +45,13 @@
#define ICACHE_SIZE 0x4000 /* instruction - 16k */
#define DCACHE_SIZE 0x2000 /* data - 8k */
+#undef CACR_EUSP /* not available on 5407 */
+ /*
+ * From MCF5407 ColdFire User’s Manual :
+ * bits 7-0 must be cleared; otherwise,
+ * performance may be affected.
+ */
+#define CACR_EUSP 0
This all seems rather sneaky. I think we would be better off
making the fact that the 5407 doesn't use CACR_EUSP more explicit
with something like:
#if defined(CONFIG_M5407)
#define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC)
#else
#define CACHE_MODE
(CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC+CACR_EUSP)
#endif
Regards
Greg
------------------------------------------------------------------------
Greg Ungerer -- Principal Engineer EMAIL: g...@snapgear.com
SnapGear Group, McAfee PHONE: +61 7 3435 2888
8 Gardner Close, FAX: +61 7 3891 3630
Milton, QLD, 4064, Australia WEB: http://www.SnapGear.com
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