>From MCF5407 ColdFire User’s Manual :
[bits 7-0] must be cleared; otherwise, performance may be affected.
Signed-off-by: Philippe De Muyter <p...@macqel.be>
---
arch/m68k/include/asm/m54xxacr.h | 11 +++++++++--
1 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h
index 27cd530..a248b23 100644
--- a/arch/m68k/include/asm/m54xxacr.h
+++ b/arch/m68k/include/asm/m54xxacr.h
@@ -26,7 +26,9 @@
#define CACR_IHLCK 0x00000800 /* Intruction cache half lock */
#define CACR_IDCM 0x00000400 /* Intruction cache inhibit */
#define CACR_ICINVA 0x00000100 /* Invalidate instr cache */
-#define CACR_EUSP 0x00000020 /* Enable separate user a7 */
+#if defined(CONFIG_M54xx)
+#define CACR_EUSP 0x00000020 /* Enable separate user a7 */
+#endif
#define ACR_BASE_POS 24 /* Address Base */
#define ACR_MASK_POS 16 /* Address Mask */
@@ -68,7 +70,12 @@
/* Enable data store buffer */
/* outside ACRs : No cache, precise */
/* Enable instruction+branch caches */
-#define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC+CACR_EUSP)
+#define _CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC)
+#if defined(CONFIG_M5407)
+#define CACHE_MODE (_CACHE_MODE)
+#else
+#define CACHE_MODE (_CACHE_MODE+CACR_EUSP)
+#endif
#define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_WT)
--
1.7.1
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