On 08/08/12 04:44, Lennart Sorensen wrote:
On Mon, Aug 06, 2012 at 09:59:40AM +0200, Michael Schnell wrote:
Yep. I suppose the addressing mode restriction might in fact be the
problem I see.
The examples I observed were setting bits in memory
(hardware-addressing mode: read-modify write a memory cell in a
single instruction) and moving a value from memory to memory
(hardware-addressing mode: read-modify write two memory cells in a
single instruction). Both access memory twice in a single
instruction. Exactly this might be optimized out when moving from
68K instruction set to Coldfire instruction set in order to reduce
the processor hardware complexity.
The FIDO processor I use does provide these addressing modes. But in
fact, Innovasic does not provide a list of cycle counts for the
instructions. So maybe the compiler even is right not to use these
instructions because they use more cycles than the combination it
produces.
I wonder where you could get cycle counts for each instruction.
I remember seeing them years ago for 8085 and such, but no idea of
freescale provides them.
Most of the ColdFire SoC Reference Manuals have a section titled
"Instruction Execution Timing", which gives a pretty good run down
on instruction timing. Probably not terribly useful for any of
the older 68k class CPU's though.
Regards
Greg
------------------------------------------------------------------------
Greg Ungerer -- Principal Engineer EMAIL: g...@snapgear.com
SnapGear Group, McAfee PHONE: +61 7 3435 2888
8 Gardner Close FAX: +61 7 3217 5323
Milton, QLD, 4064, Australia WEB: http://www.SnapGear.com
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