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Today's Topics:
1. Phase coherence problems using TVRX2 (Lucas Caldeira de Oliveira)
2. Re: Phase coherence problems using TVRX2 (Jason Roehm)
3. Re: [Discuss-gnuradio] Recording continuous I-Q stream and
frequency offset with an external reference clock (Nazmul Islam)
4. N210 USRP FPGA Programming (Samuel Ibarra)
5. Re: N210 USRP FPGA Programming (Ian Buckley)
6. Re: N210 USRP FPGA Programming (Samuel Ibarra)
7. Re: N210 USRP FPGA Programming (Ian Buckley)
----------------------------------------------------------------------
Message: 1
Date: Wed, 13 Jun 2012 15:06:43 -0300
From: Lucas Caldeira de Oliveira <[email protected]>
To: [email protected]
Subject: [USRP-users] Phase coherence problems using TVRX2
Message-ID:
<camzfunncgjocr4bm9vwmxgpy1u8oodaja+xryalu8znvmqz...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
Hi,
I'm working on a project that uses a linear array with four antennas for
direction of arrival measurement. In this scenario, phase-coherency between
each antenna is necessary.
I'm using one USRP rev4.5 with two TVRX2 rev1.1. I found that a random
phase offset is occuring every time i execute the program. After LO lock,
the phase offset remains constant.
Inside FPGA, the phase accumulator is the same for four DDCs. These signals
between the input of ADC and inside GNURadio are phase coherent. This
random phase offset is occuring inside TVRX2.
I'm using the last version of UHD and GNURadio.
Could you give us information about this problem? Is it possible to achieve
phase coherency between these signals? Is there any limitation in TVRX2
about this?
Thanks,
Lucas
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Message: 2
Date: Wed, 13 Jun 2012 14:10:41 -0400
From: Jason Roehm <[email protected]>
To: [email protected]
Subject: Re: [USRP-users] Phase coherence problems using TVRX2
Message-ID: <[email protected]>
Content-Type: text/plain; charset="iso-8859-1"; Format="flowed"
The receivers inside of the TVRX2s contain individual local oscillators
that can be fed with phase-coherent references. These LOs are typically
implemented using fractional-N frequency synthesizers, which have a
phase offset ambiguity (there are multiple stable lock points, each with
their own phase offsets). This means that if you have a few TVRX2
devices that are fed with coherent references, the output phase of their
various local oscillators will not necessarily be in phase with one
another, as you observed. This is a pretty common issue, not limited to
the TVRX2. One way of working around it is to include a calibration
source into your system that you can selectively enable to measure the
channel-to-channel phase offset.
Jason
On 06/13/2012 02:06 PM, Lucas Caldeira de Oliveira wrote:
> Hi,
>
> I'm working on a project that uses a linear array with four antennas
> for direction of arrival measurement. In this scenario,
> phase-coherency between each antenna is necessary.
>
> I'm using one USRP rev4.5 with two TVRX2 rev1.1. I found that a random
> phase offset is occuring every time i execute the program. After LO
> lock, the phase offset remains constant.
>
> Inside FPGA, the phase accumulator is the same for four DDCs. These
> signals between the input of ADC and inside GNURadio are phase
> coherent. This random phase offset is occuring inside TVRX2.
>
> I'm using the last version of UHD and GNURadio.
>
> Could you give us information about this problem? Is it possible to
> achieve phase coherency between these signals? Is there any limitation
> in TVRX2 about this?
>
> Thanks,
>
> Lucas
>
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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Message: 3
Date: Wed, 13 Jun 2012 14:29:12 -0400
From: Nazmul Islam <[email protected]>
To: John Malsbury <[email protected]>
Cc: [email protected], GNURadio Discussion List
<[email protected]>
Subject: Re: [USRP-users] [Discuss-gnuradio] Recording continuous I-Q
stream and frequency offset with an external reference clock
Message-ID:
<CAFtrfEYCL-ruFLCj=Y_=ByhmODJk-+SN3HsvxNYTqsPu-=p...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
John,
Thanks a lot for your email. My previous USRP2 modules had some old
daughterboards. I am currently working with USRP N210. I am not sure even
this one is getting the external reference, either. Couple of things:
1. I have the tools to probe the 10 MHz reference signal. But I did not
find R523 :S. I can see R521, R522, R524, C523, etc. But I did not see R523
in USRO N210.
2. I have kept the J510 jumper at 1-2. Therefore, it should take signal
from external reference clock instead of GPS.
3. When I use the "external" clock source option in UHD:USRP Sink block of
gnuradio-companion, the E led turns off. On the other hand, if I transmit
with "default" clock source option in UHD: USRP sink block, the E led turns
on !!! It's very surprising !
4. I did another experiment to check if the USRP is locked to the external
reference. At first, I gave an input of 10 MHz sine wave as an external
source and transmitted a signal at 700 MHz carrier frequency. The carrier
frequency option was given at gnuradio-companion software. Thereafter, I
varied the reference clock frequency slightly (from 10 to 10.3, 10.4 MHz,
etc.). During this period, I observed the signal at my laboratory spectrum
analyzer. If there was a fixed gain that converted the 10 MHz reference
source to 700 MHz carrier frequency, the transmitted signal's center
frequency would have shifted from 700 MHz because the fixed gain would
multiply 10.1 instead of 10 now. However, the center frequency did not
change.
I suspect that my USRP is still locked to its internal clock source. Since
this happened to two different USRP's, the issue might be in software. Has
anyone used external clock source from a gnuradio-companion generated
python code? I am changing the external clock reference source in GRC. Do I
need to make any other change?
Thanks a lot for your help.
Nazmul
On Fri, Jun 8, 2012 at 12:53 PM, John Malsbury <[email protected]>wrote:
> Nazmul,
>
> Do you have the tools(o-scope) and capacity to probe the 10 MHz reference
> signal at various places? Looking at the schematic, it looks like R523 is
> a good place to determine if the 10 MHz reference is a good place. If you
> don't see the external reference across this resistor, there may be a
> problem with the reference input or conditioning circuitry. If we
> eliminate this as a possibility we can investigate some others...
>
> -John
>
>
>
>
--
Muhammad Nazmul Islam
Graduate Student
Electrical & Computer Engineering
Wireless Information & Networking Laboratory
Rutgers, USA.
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Message: 4
Date: Wed, 13 Jun 2012 14:58:54 -0700
From: Samuel Ibarra <[email protected]>
To: [email protected]
Subject: [USRP-users] N210 USRP FPGA Programming
Message-ID:
<CAFYHLUqP1QbKqr8Vu4ekg+MDKSDMdk+ZWqj=vxgbbhfp7ug...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
Hello
I am currently working on the USRP N210. I am trying to modify the Verilog
code for the FPGA in order to gain acccess to some of the pins. I have
started to go over some of the source code provided in the uhd folder, but
I am unsure of how to do this. I was wondering if anyone had any advice on
how to do this? I would greatly appreciate any help. Thank you.
Sam
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Message: 5
Date: Wed, 13 Jun 2012 15:09:00 -0700
From: Ian Buckley <[email protected]>
To: Samuel Ibarra <[email protected]>
Cc: [email protected]
Subject: Re: [USRP-users] N210 USRP FPGA Programming
Message-ID: <[email protected]>
Content-Type: text/plain; charset=us-ascii
Sam,
If you can expand on what pins exactly and perhaps your broad goals then I can
give you a much better answer than something broad and generic.
-Ian
On Jun 13, 2012, at 2:58 PM, Samuel Ibarra wrote:
> Hello
> I am currently working on the USRP N210. I am trying to modify the Verilog
> code for the FPGA in order to gain acccess to some of the pins. I have
> started to go over some of the source code provided in the uhd folder, but I
> am unsure of how to do this. I was wondering if anyone had any advice on how
> to do this? I would greatly appreciate any help. Thank you.
> Sam
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
------------------------------
Message: 6
Date: Wed, 13 Jun 2012 16:22:44 -0700
From: Samuel Ibarra <[email protected]>
To: Ian Buckley <[email protected]>, usrp-users
<[email protected]>
Subject: Re: [USRP-users] N210 USRP FPGA Programming
Message-ID:
<CAFYHLUqttAvx8FyGLSPnDBZhvNzWXrF5QMdKC6=bfm90ozt...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
Hello Ian,
Thank you for your response. I want to be able to control pins 5, 7, 9,...
, and 35 on the J401 component on the N210 (Pins G4, F5, H6, ..., and K6 on
the FPGA). From the Basic_Tx/Rx daughterbaord schematic, I was able to see
that some of these pins are not really used on the daughterboard. I am
working on implementing a MAC protocol that will be using a number
directional antennas to send our information. I wanted to use these pins in
order to select the antenna direction needed for the communication. Is
something like this possible? Thank you for your time and help.
Sam
On Wed, Jun 13, 2012 at 3:09 PM, Ian Buckley <[email protected]> wrote:
> Sam,
> If you can expand on what pins exactly and perhaps your broad goals then I
> can give you a much better answer than something broad and generic.
> -Ian
>
> On Jun 13, 2012, at 2:58 PM, Samuel Ibarra wrote:
>
> > Hello
> > I am currently working on the USRP N210. I am trying to modify the
> Verilog code for the FPGA in order to gain acccess to some of the pins. I
> have started to go over some of the source code provided in the uhd folder,
> but I am unsure of how to do this. I was wondering if anyone had any advice
> on how to do this? I would greatly appreciate any help. Thank you.
> > Sam
> > _______________________________________________
> > USRP-users mailing list
> > [email protected]
> > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
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Message: 7
Date: Wed, 13 Jun 2012 17:47:54 -0700
From: Ian Buckley <[email protected]>
To: Samuel Ibarra <[email protected]>
Cc: usrp-users <[email protected]>
Subject: Re: [USRP-users] N210 USRP FPGA Programming
Message-ID: <[email protected]>
Content-Type: text/plain; charset="us-ascii"
Sam,
You are probably in luck on this one, it sounds like you just need to bit-bang
those pins with firmware for your application, and all the H/W hooks exist to
do this already.
The relevant firmware calls are (should be) hal_gpio_* and you can find them in
firmware/zpu/lib/hal* though I don't see the definitions in my tree...nor any
references to the registers in memory_map.h...perhaps Josh/John/etc can comment
on that.
In H/W there are 5 registers that control these pins on the daughter board RX
and TX connectors, the verilog is in gpio_atr.v.
Very briefly it works as follows: One 32bit register controls the direction of
each of the 32 signals, 1 control bit per signal. The other 4 32bit registers
establish the values of every signal set to an output (inputs would just be
"don't care") for 4 different H/W states,
IDLE, TX, RX and FULL DUPLEX. This means that the daughter board antenna
switches are controlled by hardware state changes, rather than "real time"
firmware. Thus if you want to drive values to the GPIO, independent of these
H/W states, read-modify-write the same bits in all 4 registers.
I'll assume you can work out the rest from here out by looking at the code. You
may have to write your own HAL support, but it shouldn't be hard. One note of
caution: On some daughter boards possibly writing the wrong values to these
registers might cause the TX to drive the RX in the radio at damaging power
level's..look at the schematics and your code carefully!
-Ian
On Jun 13, 2012, at 4:22 PM, Samuel Ibarra wrote:
> Hello Ian,
>
> Thank you for your response. I want to be able to control pins 5, 7, 9,... ,
> and 35 on the J401 component on the N210 (Pins G4, F5, H6, ..., and K6 on the
> FPGA). From the Basic_Tx/Rx daughterbaord schematic, I was able to see that
> some of these pins are not really used on the daughterboard. I am working on
> implementing a MAC protocol that will be using a number directional antennas
> to send our information. I wanted to use these pins in order to select the
> antenna direction needed for the communication. Is something like this
> possible? Thank you for your time and help.
>
> Sam
>
> On Wed, Jun 13, 2012 at 3:09 PM, Ian Buckley <[email protected]> wrote:
> Sam,
> If you can expand on what pins exactly and perhaps your broad goals then I
> can give you a much better answer than something broad and generic.
> -Ian
>
> On Jun 13, 2012, at 2:58 PM, Samuel Ibarra wrote:
>
> > Hello
> > I am currently working on the USRP N210. I am trying to modify the Verilog
> > code for the FPGA in order to gain acccess to some of the pins. I have
> > started to go over some of the source code provided in the uhd folder, but
> > I am unsure of how to do this. I was wondering if anyone had any advice on
> > how to do this? I would greatly appreciate any help. Thank you.
> > Sam
> > _______________________________________________
> > USRP-users mailing list
> > [email protected]
> > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
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