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Today's Topics:
1. Re: Phase coherence problems using TVRX2 (John Malsbury)
2. DC value (Sanat Gulvadi)
3. Re: Phase coherence problems using TVRX2
(Lucas Caldeira de Oliveira)
4. Re: N210 USRP FPGA Programming (Ian Buckley)
5. Basic Questions about DDC and Sampling Rate (Alex The Great)
6. Re: Basic Questions about DDC and Sampling Rate (John Malsbury)
----------------------------------------------------------------------
Message: 1
Date: Thu, 14 Jun 2012 09:29:02 -0700
From: John Malsbury <[email protected]>
To: [email protected]
Subject: Re: [USRP-users] Phase coherence problems using TVRX2
Message-ID: <[email protected]>
Content-Type: text/plain; charset="iso-8859-1"; Format="flowed"
Lukas,
I forgot to mention that we do have a new knowledge base up. There is a
document you'll find there that explains the requirements for a MIMO
system that can be used for direction of arrival measurements.
I recommend taking a look: www.ettus.com/kb
Search "MIMO" if you can't find the document in the menus.
Cheers,
John Malsbury
On 06/13/2012 11:06 AM, Lucas Caldeira de Oliveira wrote:
> Hi,
>
> I'm working on a project that uses a linear array with four antennas
> for direction of arrival measurement. In this scenario,
> phase-coherency between each antenna is necessary.
>
> I'm using one USRP rev4.5 with two TVRX2 rev1.1. I found that a random
> phase offset is occuring every time i execute the program. After LO
> lock, the phase offset remains constant.
>
> Inside FPGA, the phase accumulator is the same for four DDCs. These
> signals between the input of ADC and inside GNURadio are phase
> coherent. This random phase offset is occuring inside TVRX2.
>
> I'm using the last version of UHD and GNURadio.
>
> Could you give us information about this problem? Is it possible to
> achieve phase coherency between these signals? Is there any limitation
> in TVRX2 about this?
>
> Thanks,
>
> Lucas
>
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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Message: 2
Date: Thu, 14 Jun 2012 19:01:51 +0200
From: Sanat Gulvadi <[email protected]>
To: [email protected]
Subject: [USRP-users] DC value
Message-ID:
<CAH12yLtJR=_ygrw8-wrx00ncw2+h-z75dgisb1sa0rogi3o...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
Good Evening,
I have an OFDM based communication system in which I use a UHD application
to communicate between 2 USRP2 devices. I notice from my received data that
there is a small attenuation in the subcarriers which are relatively in the
middle of the band. The QAM points in the constellation are drawn towards
the point (0,0) of the constellation. Could this be because of a DC value ?
How do I avoid this or maybe push the DC out of my band of interest ? In
one of my previous questions, it was suggested that I use offset tuning.
How do I do this ?
Also, each of the 4, 4-QAM "clouds" have are "spread" to an extent.
Sometimes this spread is very less and almost unnoticeable, sometimes quite
large but still enough to keep all the points in their correct quadrant,
but quite often it is so large that they tend to have some points in the 2
two neighbouring quardrants and this leads to symbol errors. To illustrate
what I mean by this spread, I have a link to a rough sketch I made, since I
don't have an actual plot with me right now.
link : http://imgur.com/7g9yl
I should add that I have no external reference to synchronize the 2
devices. I have all my synchronization algorithms in the receiver. However,
when I did use a 10Mhz square wave at 10dBm from a function generator
connected to the REF inputs of the 2 devices, and run
usrp->set_clock_source("external",0), I get the E LED on the front panel to
glow, but there is no significant change. I don't have any other better
external source to generate a PPS signal simultaneously.
I understand the second part of my email is on a different topic. I'd be
grateful to get some response for both, but even just a suggestion for the
DC stuff would be great.
Have an awesome one.
Best Regards,
Sanat
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Message: 3
Date: Thu, 14 Jun 2012 14:31:38 -0300
From: Lucas Caldeira de Oliveira <[email protected]>
To: John Malsbury <[email protected]>
Cc: [email protected]
Subject: Re: [USRP-users] Phase coherence problems using TVRX2
Message-ID:
<camzfunoaq4x+xr8iejx_ouknxltr7cofmjejuh-huzrpgy3...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
Thanks for the answers. I sent this document to my project team.
Lucas
2012/6/14 John Malsbury <[email protected]>
> **
> Lukas,
>
> I forgot to mention that we do have a new knowledge base up. There is a
> document you'll find there that explains the requirements for a MIMO system
> that can be used for direction of arrival measurements.
>
> I recommend taking a look: www.ettus.com/kb
>
> Search "MIMO" if you can't find the document in the menus.
>
> Cheers,
> John Malsbury
>
>
>
>
> On 06/13/2012 11:06 AM, Lucas Caldeira de Oliveira wrote:
>
> Hi,
>
> I'm working on a project that uses a linear array with four antennas for
> direction of arrival measurement. In this scenario, phase-coherency between
> each antenna is necessary.
>
> I'm using one USRP rev4.5 with two TVRX2 rev1.1. I found that a random
> phase offset is occuring every time i execute the program. After LO lock,
> the phase offset remains constant.
>
> Inside FPGA, the phase accumulator is the same for four DDCs. These
> signals between the input of ADC and inside GNURadio are phase coherent.
> This random phase offset is occuring inside TVRX2.
>
> I'm using the last version of UHD and GNURadio.
>
> Could you give us information about this problem? Is it possible to
> achieve phase coherency between these signals? Is there any limitation in
> TVRX2 about this?
>
> Thanks,
>
> Lucas
>
>
> _______________________________________________
> USRP-users mailing
> [email protected]http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
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Message: 4
Date: Thu, 14 Jun 2012 12:25:09 -0700
From: Ian Buckley <[email protected]>
To: usrp-users forum <[email protected]>
Subject: Re: [USRP-users] N210 USRP FPGA Programming
Message-ID: <[email protected]>
Content-Type: text/plain; charset="us-ascii"
Sam,
A quick follow up. I discussed this very briefly this AM with Josh. There are
no direct references to these registers in the current ZPU firmware because
they are only accessed from UHD on the host in production. I glanced at that
code quickly:
uhd/host/lib/usrp/usrp2/usrp2_regs.hpp contains a base address for them:
#define SR_GPIO 184
uhd/host/lib/usrp/dboard_iface.cpp defines some methods to access them.
-Ian
----
Sam,
You are probably in luck on this one, it sounds like you just need to bit-bang
those pins with firmware for your application, and all the H/W hooks exist to
do this already.
The relevant firmware calls are (should be) hal_gpio_* and you can find them in
firmware/zpu/lib/hal* though I don't see the definitions in my tree...nor any
references to the registers in memory_map.h...perhaps Josh/John/etc can comment
on that.
In H/W there are 5 registers that control these pins on the daughter board RX
and TX connectors, the verilog is in gpio_atr.v.
Very briefly it works as follows: One 32bit register controls the direction of
each of the 32 signals, 1 control bit per signal. The other 4 32bit registers
establish the values of every signal set to an output (inputs would just be
"don't care") for 4 different H/W states,
IDLE, TX, RX and FULL DUPLEX. This means that the daughter board antenna
switches are controlled by hardware state changes, rather than "real time"
firmware. Thus if you want to drive values to the GPIO, independent of these
H/W states, read-modify-write the same bits in all 4 registers.
I'll assume you can work out the rest from here out by looking at the code. You
may have to write your own HAL support, but it shouldn't be hard. One note of
caution: On some daughter boards possibly writing the wrong values to these
registers might cause the TX to drive the RX in the radio at damaging power
level's..look at the schematics and your code carefully!
-Ian
On Jun 13, 2012, at 4:22 PM, Samuel Ibarra wrote:
> Hello Ian,
>
> Thank you for your response. I want to be able to control pins 5, 7, 9,... ,
> and 35 on the J401 component on the N210 (Pins G4, F5, H6, ..., and K6 on the
> FPGA). From the Basic_Tx/Rx daughterbaord schematic, I was able to see that
> some of these pins are not really used on the daughterboard. I am working on
> implementing a MAC protocol that will be using a number directional antennas
> to send our information. I wanted to use these pins in order to select the
> antenna direction needed for the communication. Is something like this
> possible? Thank you for your time and help.
>
> Sam
>
> On Wed, Jun 13, 2012 at 3:09 PM, Ian Buckley <[email protected]> wrote:
> Sam,
> If you can expand on what pins exactly and perhaps your broad goals then I
> can give you a much better answer than something broad and generic.
> -Ian
>
> On Jun 13, 2012, at 2:58 PM, Samuel Ibarra wrote:
>
> > Hello
> > I am currently working on the USRP N210. I am trying to modify the Verilog
> > code for the FPGA in order to gain acccess to some of the pins. I have
> > started to go over some of the source code provided in the uhd folder, but
> > I am unsure of how to do this. I was wondering if anyone had any advice on
> > how to do this? I would greatly appreciate any help. Thank you.
> > Sam
> > _______________________________________________
> > USRP-users mailing list
> > [email protected]
> > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
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Message: 5
Date: Thu, 14 Jun 2012 18:04:11 -0400
From: Alex The Great <[email protected]>
To: [email protected]
Subject: [USRP-users] Basic Questions about DDC and Sampling Rate
Message-ID:
<cap-jvcey5-ri6onvjyg6r0kf4kgcynikyfoxhpvwqh0+vdy...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
Hi, I'm having trouble with the basics here.
I'm using the N210 with the SBX daughterboard.
Please tell me if my logic is correct:
The USRP N210 has 100 MHz bandwidth.
I can decimate at a minimum of 8, and at a maximum of 256.
Thus the maximum amount of data I can send from the USRP to the PC is 100e6
/ 8 = 12.5 Msps.
The minimum is therefore 100e6 / 256 = 390.625 ksps.
If my samples are 4 bytes large, then the min and max amounts of data being
sent to the PC is 1562.5 kBps and 50 MBps.
I am still not understanding how these factors come into play:
Is there a minimum amount of data that must be sent from the USRP to the PC
per second?
How does the sampling rate relate to decimation in the DDC?
The maximum sampling rate is 25 Msps (determined by the GigE interface?).
The SBX has 40 MHz bandwidth. Does this mean that out of the 100 MHz
bandwidth of the USRP, only 40 MHz is usable?
Please correct me in any place I am wrong.
Sorry for the newbie questions, but I really want to understand.
-N
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Message: 6
Date: Thu, 14 Jun 2012 15:06:34 -0700
From: John Malsbury <[email protected]>
To: [email protected]
Subject: Re: [USRP-users] Basic Questions about DDC and Sampling Rate
Message-ID: <[email protected]>
Content-Type: text/plain; charset=ISO-8859-1; format=flowed
Maximum rate is 25 MS/s in 16-bit mode, and 50 MS/s in 8-bit mode. I
think it goes down to 250 ks/s. With the UHD you only need to specify
sample rate, not interp/decim factors.
With the 40 MHz baseband filter of the SBX, only 40 MHz is usable.
-John Malsbury
On 06/14/2012 03:04 PM, Alex The Great wrote:
> Thus the maximum amount of data I can send from the USRP to the PC is
> 100e6 / 8 = 12.5 Msps.
------------------------------
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