I can answer the question related to the padding. I am not sure about the rest.
Ettus Padding: An ethernet frame has 6 bytes of destination MAC address and 6 bytes of Source MAC address. Since we use 64 bits/8 bytes of data in one clock cycle, we add a 6 byte padding in front of the ethernet packet. The new packet becomes: < 6 bytes padding> 80 00 20 7A 3F 3E 80 00 20 20 and so on... [image: Inline image 1] We just ignore the 6 bytes of padding in the eth_dispatch block. It is used to align the incoming packet to make classification easier. - Sugandha On Tue, Nov 28, 2017 at 12:09 PM, Christian Lenz < christian.l...@freedelity.com> wrote: > Ian and Sugandha, > > thank you very much for your comments and also for the attached file. > Sadly, another three questions remain for the moment: > 1. In the attached file, there is a series of 48? bits named "Ettus > Padding". Is this an Ettus specific bit sequence and where can I find > information on this? > 2. If powering up and programming the FPGA, the clock from the PLL is not > present because it must be programmed over SPI first. According to the HDL > source files and pin constraints, the corresponding SPI master module in > the FPGA is clocked from a 125MHz clock. I assume this clock to be present > without any configuration, is this true? > 3. Do you know where to find the missing pages of the X3xx schematics > document (13-17)? I would assume to find the 125MHz clock source on page 17. > > Thanks a lot! > > Zitat von Ian Buckley <i...@ianbuckley.net>: > > > Christian, >> CHDR packets are encapsulated in UDP/IP between Host and USRP. See the >> attachment. >> >> PHY+ MAC functionality live under the x300_sfpp_io_core. However these >> blocks do not encapsulate/decapsulate the network packets. >> All the ethernet/IP/UDP framing fields are added by chdr_eth_framer on >> egress, and will be removed on ingress by etc_dispatch (if needed). >> >> -Ian >> > > > > -- Sugandha Gupta Staff Software Engineer Ettus Research
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