Hi Brendon, and usrp-users (adding the mailing list back to the conversation),
This sounds like a problem with the makefile setup. You'll want to check that your sources are correctly added to the DESIGN_SRCS variable in your testbench Makefile (see below for reference...). Directories variables all need to point to the correct place (your equivalent RFNOC_OOTEXAMPLE_DIR is set up correctly in the testbench Makefile and used correctly in the ip/<name>/Makefile.inc). One thing I'll do to help debug is use makefile warnings. For example, this should print out the .xci file source location when building. (If it's blank, or not there, something's definitely wrong) ``` RFNOC_OOTEXAMPLE_DIR = $(abspath ../../) # Include makefiles and sources for all IP components # *after* defining the LIB_IP_DIR include $(RFNOC_OOTEXAMPLE_DIR)/ip/complex_to_magphase_oot/Makefile.inc DESIGN_SRCS += $(abspath \ $(LIB_IP_COMPLEX_TO_MAGPHASE_OOT_SRCS) \ $(warning $(LIB_IP_COMPLEX_TO_MAGPHASE_OOT_SRCS)) ) ``` Hope this helps, EJ On Fri, Jul 27, 2018 at 8:09 AM Chetwynd, Brendon - 0551 - MITLL < brendon.chetw...@ll.mit.edu> wrote: > EJ, > > > > Thanks for the repo. I was able to successfully get it up and running > with your example. > > > > I am attempting to add my own module with two Xilinx IP blocks (one > CORDIC, one Data Width Converter). > > > > Any sort of gotchas I should be worried about? I have modified the > scripts in what seems like a logical fashion, but when attempting to > simulate the modules do not get properly elaborated (interesting enough I > see my new module being compiled and elaborated, but when simulation begins > the scripts complain about not finding the module. > > > > Thanks, > > Brendon > > > > > ============================================================================ > > Brendon Chetwynd Technical > Staff > > MIT Lincoln Laboratory > > Cyber Systems and Operations (Group > 51) > > > > 244 Wood Street Lexington, MA > 02420-9185 > > 781-981-8212 > (office) > > brendon.chetw...@ll.mit.edu 781-879-4635 (cell) > > 781-387-3030 (pager) > > 781-981-7548 (fax) > > > ============================================================================ > > > > *From:* EJ Kreinar <ejkrei...@gmail.com> > *Sent:* Saturday, July 21, 2018 6:59 PM > *To:* Neel Pandeya <neel.pand...@ettus.com> > *Cc:* Chetwynd, Brendon - 0551 - MITLL <brendon.chetw...@ll.mit.edu>; > USRP-users@lists.ettus.com > *Subject:* Re: [USRP-users] RFNoc Blocks with Xilinx IP > > > > Hi Brendon, > > > > I went ahead and updated the OOT example repo to be compatible with Vivado > 2017.4 and the uhd-fpga "master" branch: > https://github.com/ejk43/rfnoc-ootexample > > > > The simulation testbenches now run using uhd-fpga master. Let me know if > this works for you. Thanks! > > EJ > > > > On Fri, Jul 20, 2018 at 1:01 PM EJ Kreinar <ejkrei...@gmail.com> wrote: > > Hi Brendon, > > > > I have an example repo that shows how to use out-of-tree makefiles with > xilinx IP (.xci definitions): github.com/ejk43/rfnoc-ootexample > > > > Please feel free to copy this format- a few other rfnoc developers on the > mailing list indicated it has worked for them too. > > > > Note that the rfnoc blocks are currently targeting the uhd-fpga source > code as of Vivado 2015.4, and the testbenches will NOT currently run > against most recent uhd-fpga and Vivado 2017.4. I would really appreciate a > PR to update the IP to use vivado 2017.4 and noc blocks with the new inputs > to the noc_shell :) I'll update it "eventually" but no idea when exactly. > > > > Hope this helps! Looking forward to seeing your OOT fpga blocks :) > > > > EJ > > > > On Fri, Jul 20, 2018, 12:19 PM Neel Pandeya via USRP-users < > usrp-users@lists.ettus.com> wrote: > > Hello Brendon: > > > > Could you describe in more detail what you're trying to do, or how you > want to add your Xilinx IP? > > > > Are you still using "rfnocmodtool" to add your custom RFNoC blocks? > > > > The flow described in that document, and in the Application Note below, is > the primary/intended way to add IP to an RFNoC installation. > > > > https://kb.ettus.com/Getting_Started_with_RFNoC_Development > > > > Please note that you should use the head of the UHD master branch, not the > "rfnoc-devel" branch, when using RFNoC. > > > > --​Neel Pandeya > > > > > > > > > > On 20 July 2018 at 07:01, Chetwynd, Brendon - 0551 - MITLL via USRP-users < > usrp-users@lists.ettus.com> wrote: > > I have been following the following blog post: > > > > > http://www.synchronouslabs.com/blog/creating-a-custom-rfnoc-block-with-using-xillinx-ip > > > > Near the end, it instructs the user to add the Xilinx IP files (.xci for > example) to the UHD project directory. > > > > However, as this is a clone of the Ettus Research repo ( > https://github.com/EttusResearch/fpga.git), I am wondering if there is > another way to do it that is compliant with the RFNOC build process. > > > > Specifically, I would like to drop my customized Xilinx IP within my own > rfnoc repository. > > > > Any advice? > > > > Thanks, > > Brendon > > > > > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > >
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