It is definitely regenerated, and I can believe that there's no
compensation for delay. I haven't measured the output on a phase noise
analyzer, but as it's coming from the same clock generator which provides
the sample clock for the device I would expect it to be similarly clean.

Nick

On Tue, Oct 16, 2018 at 9:07 AM Marcus D. Leech <mle...@ripnet.com> wrote:

> On 10/16/2018 12:00 PM, Nick Foster wrote:
>
> Wait, what? I've been using REF OUT for years now. What am I missing? What
> does "aren't actually fully supported" mean?
>
> My understanding, and R&D can correct me if I'm wrong, is that the REF OUT
> not only has no phase-length compensation, but it's
>   a regenerated signal with unpleasant phase-noise.
>
> But if those issues have been addressed, then I retract my statement.
>
>
>
> On Tue, Oct 16, 2018 at 8:57 AM Marcus D. Leech via USRP-users <
> usrp-users@lists.ettus.com> wrote:
>
>> On 10/16/2018 07:44 AM, Francois Quitin via USRP-users wrote:
>>
>> Dear all,
>>
>>
>>
>> We encountered a small problem when we try to build a 4-element MIMO
>> array with two X310 (equipped with UBX daughterboards). We are working on
>> UHD-3.10.3:
>>
>> -          When we use an octoclock to provide the 10 MHz Ref and the
>> PPS to both X310, the phase of each receiving front-end stays nicely
>> constant (see octoclock.png). The Ref Source and Time Source are set to
>> “external” in GNU Radio (the points represent a measurement taken every ten
>> seconds)
>>
>> -          When we use the 10 MHz Ref Out and PPS Out from one X310 and
>> feed it to the Ref In and PPS In of the other X310, we observe a drift in
>> the phases of the channels from the second X310. This is shown in the graph
>> daisyChain.png, where we take one point every ten seconds. We configured
>> GNU Radio to set the Ref Source and Time source of the first USRP to
>> “default”, the ones of the second USRP to “external”.
>>
>>
>>
>> This drift is something more severe, sometimes less, but it’s always
>> present. Any idea why we observe this?
>>
>>
>>
>> Many thanks,
>>
>>
>>
>> François
>>
>>
>>
>> ---
>>
>> Francois QUITIN
>>
>> Assistant Professor
>>
>>
>>
>> BEAMS Dpt. – Embedded Electronics
>>
>> Brussels School of Engineering
>>
>> Université Libre de Bruxelles (ULB)
>>
>>
>>
>> Web   https://sites.google.com/site/fquitin2/
>>
>> Phone +32 2 650 2829 <+32%202%20650%2028%2029>
>>
>>
>>
>> The REF OUT and PPS OUT ports aren't actually fully supported in the FPGA
>> code, and we don't, at this point, recommend their use.
>>
>>
>>
>> _______________________________________________
>> USRP-users mailing list
>> USRP-users@lists.ettus.com
>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>
>
>
_______________________________________________
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

Reply via email to