Hello everyone,
I am implementing the system on USRP X310 where the maximum sampling rate
needs to be used on both Rx channels, so in total ( 2 (IQ) x 2 (RF cards) x
200 MSPs).
After doing tests of throughput between USRP and PC, I experience that
there will be bottleneck related to writing samples in memory of PC (I am
using SSD).
This is also confirmed by numerous previous post on the usrp mailing list.
Before I describe what is my question and idea, I will shortly describe
system requirements.
My system needs to sample data periodically as I am sending bursts of data
from time to time.
One burst sent from Tx can have a duration of 6-10ms, then there is a gap
of 10 ms, after which I am again sending a burst of data (signal).
So in short, I would have at maximum 10 ms of data then gap of 10ms (or
more if needed) sampled at highest X310 sampling rate 800MSPs.
My idea is to develop RFNoC CE for burst detection (the burst contains
preamble with good correlation properties).
This RFNoC CE would indicate when there are valuable samples available for
streaming to PC.
Therefore, my idea would be to stream only samples that correspond to a
valuable signal to PC.
In the worst case, I would have ~16MB of data to transfer every 10ms (this
would result in throughput of ~1.6GB/s).
Saving 16MB of data in BRAM might not be a good approach.
Therefore I would like to save 16MB in DRAM (DDR3) memory, and from DDR3
Stream data to PC.
However, after reading several posts on the mailing list I am confused if
there are already available block which
could support me in the development of DRAM FIFO controlled by the burst
detector.
I am aware of RFNoC reply functionality for Tx side, however, I am not
aware if there is an example where samples are
streamed from DRAM to PC.
Summarizing my goal in the logical diagram:
|Radio Block| ------------> |Burst Detector|
| |
| YES/NO |
/<------------------
|--------------------->|DRAM
FIFO|--------------->|PCIe|
My questions would:
1. What is the maximum writing speed to DRAM on X310?
2. Are they already available RFNoC block which would support the
development of controlled DRAM FIFO?
3. In general, if you have any useful comments, guidelines please let me
know.
Thanks a lot,
Emil
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