Sorry for the late answer, I was busy.
I tried that including a one second sleep after it but it does not help.
Am 26.04.2019 um 18:30 schrieb Marcus D. Leech via USRP-users:
On 04/26/2019 12:07 PM, Fabian Schwartau via USRP-users wrote:
Ohh.. you are right, I did not do that in the example code. But the
problem is the same in my main application, where I do. As I said, the
180° phase shift is probably somehow related and not that easy to
reporduce. So the spectrum or I/Q swap should be the main issue here
and I hope that this will also solve the 180° phase swap.
Interestingly the phase is correct, if I set the frequency twice for
each channel with a little delay in between.
Could you try something? Insert a set_time_next_pps() into the code in
initalization--this should align the TOD clocks in both internal DSP radio
modules.
Am 26.04.2019 um 18:02 schrieb Marcus D. Leech via USRP-users:
On 04/26/2019 11:36 AM, Fabian Schwartau via USRP-users wrote:
Hi,
I am am using LO sharing. So there should not be any phase offset
and no mirrored spectrum, no matter when the USRP comes around to
change the frequency. Even not using LO-sharing, the spectrum should
NOT be mirrored.
The apparent I/Q swap issue I agree should not happen, and I have a
query in to R&D about it.
Am 26.04.2019 um 17:12 schrieb Marcus D. Leech via USRP-users:
On 04/26/2019 05:13 AM, Fabian Schwartau via USRP-users wrote:
Hi,
a couple of days ago I filed a bug report which caused the USRPs
to switch but noone has responded yet. I did now encountered other
problems wich might be related to that issue. Can somone from
Ettus (or someone else) take a look at that?
Bug report is here: https://github.com/EttusResearch/uhd/issues/271
Best regards,
Fabian
So, the original design reason for timed-commands was to support
simultaneous tuning (and assertion of a resynch pulse) across
*multiple USRPs*,
in support of reducing/eliminating mutual phase offset among
identically-hardwared USRPs, for daughtercards that supported
phase-resynch.
When you use timed commands within a single USRP, hoping for
similar effects, you won't get them, because the commands in the queue
are *necessarily* executed sequentially. Even if there was a
"parallel execution" structure within the FPGA to handle the
commands, most of
the commands you care about ultimately end up on an SPI or I2C
bus, and those are inherently serial, and multiple devices
(synthesizers,
variable-gain amplifiers, clock-plls) typically share a single
such bus on a per-slot basis. In order to have "true parallelism"
*within* a single
USRP, you'd need dedicated control buses to each device that is
controlled by I2C/SPI/whatever, *in addition* to parallel execution
within the
FPGA.
When you're setting a bunch of PLL synthesizers sequentially, you
can expect that they won't agree on phase, even when being driven
by a common clock. The mechanism for achieving phase coherence
with TwinRx is to use LO sharing.
https://kb.ettus.com/TwinRX
This app-note talks about LO sharing with TwinRX
https://kb.ettus.com/Direction_Finding_with_the_USRP%E2%84%A2_X-Series_and_TwinRX%E2%84%A2
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