Hello all, So I have been attempting to build an X310 HG FPGA image following the steps in the getting started guide for RFNoC for a while now, and I have been getting the following error:
Starting DRC Task INFO: [DRC 23-27] Running DRC with 8 threads ERROR: [DRC MDRV-1] Multiple Driver Nets: Net bus_clk_gen/inst/CLK_OUT4 has multiple drivers: bus_clk_gen/inst/clkout4_buf/O, and radio_clk_gen/inst/clkout1_buf/O. ERROR: [DRC MDRV-1] Multiple Driver Nets: Net radio_reset_sync/reset_double_sync/synchronizer_false_path/value[9]_9 has multiple drivers: radio_reset_sync/reset_double_sync/synchronizer_false_path/stages[9].value_reg[9][0]/Q, and ce_reset_sync/reset_double_sync/synchronizer_false_path/stages[9].value_reg[9][0]/Q. INFO: [Project 1-461] DRC finished with 2 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. ERROR: [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run. Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 13791.785 ; gain = 1.887 ; free physical = 109997 ; free virtual = 117079 INFO: [Common 17-83] Releasing license: Implementation 7 Infos, 0 Warnings, 0 Critical Warnings and 3 Errors encountered. opt_design failed ERROR: [Common 17-39] 'opt_design' failed due to earlier errors. I have attached the build log for those who may want to look at it for more info. Can someone direct me in what I need to do to resolve this issue so I can build an FPGA image successfully? any help would be greatly appreciated. Best Regards, Jerrid
#----------------------------------------------------------- # Vivado v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:36:41 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 # Start of session at: Fri Dec 27 15:38:56 2019 # Process ID: 29400 # Current directory: /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-X310_RFNOC_HG # Command line: vivado -mode gui -source /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build_x300.tcl -log build.log -journal x300.jou # Log file: /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-X310_RFNOC_HG/build.log # Journal file: /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-X310_RFNOC_HG/x300.jou #----------------------------------------------------------- start_gui source /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build_x300.tcl # source $::env(VIV_TOOLS_DIR)/scripts/viv_utils.tcl ## namespace eval ::vivado_utils { ## # Export commands ## namespace export \ ## initialize_project \ ## synthesize_design \ ## check_design \ ## generate_post_synth_reports \ ## generate_post_place_reports \ ## generate_post_route_reports \ ## write_implementation_outputs \ ## get_top_module \ ## get_part_name \ ## get_vivado_mode ## ## # Required environment variables ## variable g_tools_dir $::env(VIV_TOOLS_DIR) ## variable g_top_module $::env(VIV_TOP_MODULE) ## variable g_part_name $::env(VIV_PART_NAME) ## variable g_output_dir $::env(VIV_OUTPUT_DIR) ## variable g_source_files $::env(VIV_DESIGN_SRCS) ## variable g_vivado_mode $::env(VIV_MODE) ## ## # Optional environment variables ## variable g_verilog_defs "" ## if { [info exists ::env(VIV_VERILOG_DEFS) ] } { ## set g_verilog_defs $::env(VIV_VERILOG_DEFS) ## } ## variable g_include_dirs "" ## if { [info exists ::env(VIV_INCLUDE_DIRS) ] } { ## set g_include_dirs $::env(VIV_INCLUDE_DIRS) ## } ## } ## proc ::vivado_utils::initialize_project { {save_to_disk 0} } { ## variable g_top_module ## variable g_part_name ## variable g_output_dir ## variable g_source_files ## ## variable bd_files "" ## ## file delete -force $g_output_dir/build.rpt ## ## if {$save_to_disk == 1} { ## puts "BUILDER: Creating Vivado project ${g_top_module}_project.xpr for part $g_part_name" ## create_project -part $g_part_name ${g_top_module}_project ## } else { ## puts "BUILDER: Creating Vivado project in memory for part $g_part_name" ## create_project -in_memory -part $g_part_name ## } ## ## foreach src_file $g_source_files { ## set src_ext [file extension $src_file ] ## if [expr [lsearch {.vhd .vhdl} $src_ext] >= 0] { ## puts "BUILDER: Adding VHDL : $src_file" ## read_vhdl -library work $src_file ## } elseif [expr [lsearch {.v .vh .sv .svh} $src_ext] >= 0] { ## puts "BUILDER: Adding Verilog : $src_file" ## read_verilog $src_file ## } elseif [expr [lsearch {.xdc} $src_ext] >= 0] { ## puts "BUILDER: Adding XDC : $src_file" ## read_xdc $src_file ## } elseif [expr [lsearch {.xci} $src_ext] >= 0] { ## puts "BUILDER: Adding IP : $src_file" ## read_ip $src_file ## set_property generate_synth_checkpoint true [get_files $src_file] ## } elseif [expr [lsearch {.ngc .edif .edf} $src_ext] >= 0] { ## puts "BUILDER: Adding Netlist : $src_file" ## read_edif $src_file ## } elseif [expr [lsearch {.bd} $src_ext] >= 0] { ## puts "BUILDER: Adding Block Design to list (added after IP regeneration): $src_file" ## append bd_files "$src_file " ## } elseif [expr [lsearch {.bxml} $src_ext] >= 0] { ## puts "BUILDER: Adding Block Design XML to list (added after IP regeneration): $src_file" ## append bd_files "$src_file " ## } elseif [expr [lsearch {.dat} $src_ext] >= 0] { ## puts "BUILDER: Adding Data File : $src_file" ## add_files $src_file ## } else { ## puts "BUILDER: \[WARNING\] File ignored!!!: $src_file" ## } ## } ## ## # The 'synth_ip [get_ips *]' step causes builds in Windows to recompile various ## # pieces of the IP. This is time-consuming and unnecessary behavior, thus is removed. ## # These steps are redundant anyway since the IP builder performs both of them. ## # puts "BUILDER: Refreshing IP" ## # generate_target all [get_ips *] ## # synth_ip [get_ips *] ## ## #might seem silly, but we need to add the bd files after the ip regeneration. ## foreach file $bd_files { ## puts "BUILDER: Adding file from Block Design list: $file" ## add_files -norecurse $file ## } ## ## puts "BUILDER: Setting $g_top_module as the top module" ## set_property top $g_top_module [current_fileset] ## } ## proc ::vivado_utils::synthesize_design {args} { ## variable g_top_module ## variable g_part_name ## variable g_verilog_defs ## variable g_include_dirs ## ## set vdef_args "" ## foreach vdef $g_verilog_defs { ## set vdef_args [concat $vdef_args "-verilog_define $vdef"] ## } ## set incdir_args "" ## if { [string compare $g_include_dirs ""] != 0 } { ## set incdir_args "-include_dirs $g_include_dirs" ## } ## ## set synth_cmd "synth_design -top $g_top_module -part $g_part_name" ## set synth_cmd [concat $synth_cmd $vdef_args] ## set synth_cmd [concat $synth_cmd $incdir_args] ## set synth_cmd [concat $synth_cmd $args] ## puts "BUILDER: Synthesizing design" ## eval $synth_cmd ## } ## proc ::vivado_utils::check_design {args} { ## variable g_top_module ## variable g_part_name ## variable g_verilog_defs ## variable g_include_dirs ## ## set vdef_args "" ## foreach vdef $g_verilog_defs { ## set vdef_args [concat $vdef_args "-verilog_define $vdef"] ## } ## set incdir_args "" ## if { [string compare $g_include_dirs ""] != 0 } { ## set incdir_args "-include_dirs $g_include_dirs" ## } ## ## set synth_cmd "synth_design -top $g_top_module -part $g_part_name -rtl -rtl_skip_ip -rtl_skip_constraints" ## set synth_cmd [concat $synth_cmd $vdef_args] ## set synth_cmd [concat $synth_cmd $incdir_args] ## set synth_cmd [concat $synth_cmd $args] ## puts "BUILDER: Checking syntax and elaborating design" ## eval $synth_cmd ## } ## proc ::vivado_utils::generate_post_synth_reports {} { ## variable g_output_dir ## ## puts "BUILDER: Writing post-synthesis checkpoint" ## write_checkpoint -force $g_output_dir/post_synth ## puts "BUILDER: Writing post-synthesis reports" ## report_utilization -file $g_output_dir/post_synth_util.rpt ## report_utilization -hierarchical -file $g_output_dir/post_synth_util_hier.rpt ## report_drc -ruledeck methodology_checks -file $g_output_dir/methodology.rpt ## report_high_fanout_nets -file $g_output_dir/high_fanout_nets.rpt ## } ## proc ::vivado_utils::generate_post_place_reports {} { ## variable g_output_dir ## ## puts "BUILDER: Writing post-placement checkpoint" ## write_checkpoint -force $g_output_dir/post_place ## puts "BUILDER: Writing post-placement reports" ## report_clock_utilization -file $g_output_dir/clock_util.rpt ## report_utilization -file $g_output_dir/post_place_util.rpt ## report_utilization -hierarchical -file $g_output_dir/post_place_util_hier.rpt ## report_timing -sort_by group -max_paths 5 -path_type summary -file $g_output_dir/post_place_timing.rpt ## } ## proc ::vivado_utils::generate_post_route_reports {} { ## variable g_output_dir ## ## puts "BUILDER: Writing post-route checkpoint" ## write_checkpoint -force $g_output_dir/post_route ## puts "BUILDER: Writing post-route reports" ## if {[file exists "$g_output_dir/clock_util.rpt"] == 0} { ## report_clock_utilization -file $g_output_dir/clock_util.rpt ## } ## report_timing_summary -file $g_output_dir/post_route_timing_summary.rpt ## report_utilization -file $g_output_dir/post_route_util.rpt ## report_utilization -hierarchical -file $g_output_dir/post_route_util_hier.rpt ## report_power -file $g_output_dir/post_route_power.rpt ## report_drc -file $g_output_dir/post_imp_drc.rpt ## report_timing -sort_by group -max_paths 10 -path_type summary -file $g_output_dir/post_route_timing.rpt ## } ## proc ::vivado_utils::write_implementation_outputs { {byte_swap_bin 0} } { ## variable g_output_dir ## variable g_top_module ## variable g_tools_dir ## ## puts "BUILDER: Writing implementation netlist and XDC" ## write_verilog -force $g_output_dir/${g_top_module}_impl_netlist.v ## write_xdc -no_fixed_only -force $g_output_dir/${g_top_module}_impl.xdc ## puts "BUILDER: Writing bitfile" ## write_bitstream -force $g_output_dir/${g_top_module}.bit ## puts "BUILDER: Writing config bitstream" ## set binsize [expr [file size $g_output_dir/${g_top_module}.bit]/(1024*1024)] ## set binsize_pow2 [expr {int(pow(2,ceil(log($binsize)/log(2))))}] ## set bin_iface [expr $byte_swap_bin?"SMAPx32":"SMAPx8"] ## write_cfgmem -force -quiet -interface $bin_iface -format BIN -size $binsize_pow2 -disablebitswap -loadbit "up 0x0 $g_output_dir/${g_top_module}.bit" $g_output_dir/${g_top_module}.bin ## puts "BUILDER: Writing debug probes" ## write_debug_probes -force $g_output_dir/${g_top_module}.ltx ## puts "BUILDER: Writing export report" ## report_utilization -omit_locs -file $g_output_dir/build.rpt ## report_timing_summary -no_detailed_paths -file $g_output_dir/build.rpt -append ## if {! [string match -nocase {*timing constraints are met*} [read [open $g_output_dir/build.rpt]]]} { ## send_msg_id {Builder 0-0} error "The design did not satisfy timing constraints. (Implementation outputs were still generated)" ## } ## } ## proc ::vivado_utils::write_netlist_outputs { {suffix ""} } { ## variable g_output_dir ## variable g_top_module ## ## puts "BUILDER: Writing EDIF netlist and XDC" ## set filename ${g_output_dir}/${g_top_module} ## if { [expr [string length $suffix] > 0] } { ## set filename ${filename}_${suffix} ## } ## write_edif -force ${filename}.edf ## write_xdc -no_fixed_only -force ${filename}.xdc ## puts "BUILDER: Writing export report" ## report_utilization -omit_locs -file $g_output_dir/build.rpt ## report_timing_summary -no_detailed_paths -file $g_output_dir/build.rpt -append ## if {! [string match -nocase {*timing constraints are met*} [read [open $g_output_dir/build.rpt]]]} { ## send_msg_id {Builder 0-0} error "The design did not meet all timing constraints. (Implementation outputs were still generated)" ## } ## } ## proc ::vivado_utils::close_batch_project {} { ## variable g_vivado_mode ## ## if [string equal $g_vivado_mode "batch"] { ## puts "BUILDER: Closing project" ## close_project ## } else { ## puts "BUILDER: In GUI mode. Leaving project open." ## } ## } ## proc ::vivado_utils::get_top_module {} { ## variable g_top_module ## return $g_top_module ## } ## proc ::vivado_utils::get_part_name {} { ## variable g_part_name ## return $g_part_name ## } ## proc ::vivado_utils::get_vivado_mode {} { ## variable g_vivado_mode ## return $g_vivado_mode ## } # source $::env(VIV_TOOLS_DIR)/scripts/viv_strategies.tcl ## namespace eval ::vivado_strategies { ## # Export commands ## namespace export \ ## get_preset \ ## implement_design \ ## check_strategy \ ## print_strategy ## ## variable g_viv_version [version -short] ## } ## proc ::vivado_strategies::get_impl_preset {preset} { ## variable g_viv_version ## ## set strategy [dict create] ## switch -nocase $preset { ## "Default" { ## dict set strategy "opt_design.is_enabled" 1 ## dict set strategy "opt_design.directive" "Default" ## dict set strategy "post_opt_power_opt_design.is_enabled" 0 ## dict set strategy "place_design.directive" "Default" ## dict set strategy "post_place_power_opt_design.is_enabled" 0 ## dict set strategy "post_place_phys_opt_design.is_enabled" 0 ## dict set strategy "post_place_phys_opt_design.directive" "Default" ## dict set strategy "route_design.directive" "Default" ## dict set strategy "route_design.more_options" "" ## dict set strategy "post_route_phys_opt_design.is_enabled" 0 ## dict set strategy "post_route_phys_opt_design.directive" "Default" ## } ## "Performance_Explore" { ## dict set strategy "opt_design.is_enabled" 1 ## dict set strategy "opt_design.directive" "Explore" ## dict set strategy "post_opt_power_opt_design.is_enabled" 0 ## dict set strategy "place_design.directive" "Explore" ## dict set strategy "post_place_power_opt_design.is_enabled" 0 ## dict set strategy "post_place_phys_opt_design.is_enabled" 1 ## dict set strategy "post_place_phys_opt_design.directive" "Explore" ## dict set strategy "route_design.directive" "Explore" ## dict set strategy "route_design.more_options" "" ## dict set strategy "post_route_phys_opt_design.is_enabled" 0 ## dict set strategy "post_route_phys_opt_design.directive" "Explore" ## } ## "Performance_ExplorePostRoutePhysOpt" { ## dict set strategy "opt_design.is_enabled" 1 ## dict set strategy "opt_design.directive" "Explore" ## dict set strategy "post_opt_power_opt_design.is_enabled" 0 ## dict set strategy "place_design.directive" "Explore" ## dict set strategy "post_place_power_opt_design.is_enabled" 0 ## dict set strategy "post_place_phys_opt_design.is_enabled" 1 ## dict set strategy "post_place_phys_opt_design.directive" "Explore" ## dict set strategy "route_design.directive" "Explore" ## dict set strategy "route_design.more_options" "-tns_cleanup" ## dict set strategy "post_route_phys_opt_design.is_enabled" 1 ## dict set strategy "post_route_phys_opt_design.directive" "Explore" ## } ## } ## return $strategy ## } ## proc ::vivado_strategies::implement_design {strategy} { ## variable g_viv_version ## ## # Check strategy for validity and print ## vivado_strategies::check_strategy $strategy ## puts "BUILDER: Running implementation strategy with:" ## vivado_strategies::print_strategy $strategy ## ## # Optimize the current netlist. ## # This will perform the retarget, propconst, sweep and bram_power_opt optimizations by default. ## if [dict get $strategy "opt_design.is_enabled"] { ## set opt_dir [dict get $strategy "opt_design.directive"] ## opt_design -directive $opt_dir ## } ## ## # Optimize dynamic power using intelligent clock gating after optimization ## if [dict get $strategy "post_opt_power_opt_design.is_enabled"] { ## power_opt_design ## } ## ## # Automatically place ports and leaf-level instances ## set pla_dir [dict get $strategy "place_design.directive"] ## place_design -directive $pla_dir ## ## # Optimize dynamic power using intelligent clock gating after placement ## if [dict get $strategy "post_place_power_opt_design.is_enabled"] { ## power_opt_design ## } ## ## # Optimize the current placed netlist ## if [dict get $strategy "post_place_phys_opt_design.is_enabled"] { ## set pp_physopt_dir [dict get $strategy "post_place_phys_opt_design.directive"] ## phys_opt_design -directive $pp_physopt_dir ## } ## ## # Route the current design ## set rt_dir [dict get $strategy "route_design.directive"] ## puts "BUILDER: Choosing routing directive: $rt_dir" ## if {[dict get $strategy "route_design.more_options"] eq ""} { ## route_design -directive $rt_dir ## } else { ## set rt_more [dict get $strategy "route_design.more_options"] ## puts "BUILDER: Choosing additional routing options: $rt_more" ## route_design -directive $rt_dir $rt_more ## } ## ## # Optimize the current routed netlist. ## if [dict get $strategy "post_route_phys_opt_design.is_enabled"] { ## set pr_physopt_dir [dict get $strategy "post_route_phys_opt_design.directive"] ## phys_opt_design -directive $pr_physopt_dir ## } ## } ## proc ::vivado_strategies::check_strategy {strategy} { ## variable g_viv_version ## ## set strategy_options [dict keys $strategy] ## set required_options {\ ## opt_design.is_enabled \ ## opt_design.directive \ ## post_opt_power_opt_design.is_enabled \ ## place_design.directive \ ## post_place_power_opt_design.is_enabled \ ## post_place_phys_opt_design.is_enabled \ ## post_place_phys_opt_design.directive \ ## route_design.directive \ ## post_route_phys_opt_design.is_enabled \ ## post_route_phys_opt_design.directive \ ## } ## ## set invalid 0 ## foreach req $required_options { ## if [expr [lsearch $strategy_options $req] < 0] { ## puts "BUILDER: ERROR: Invalid strategy. Missing option $req" ## set invalid 1 ## } ## } ## if $invalid { ## error "Strategy check failed!" ## } ## } ## proc ::vivado_strategies::print_strategy {strategy} { ## variable g_viv_version ## ## foreach opt [dict keys $strategy] { ## set val [dict get $strategy $opt] ## puts " * $opt = $val" ## } ## } # vivado_utils::initialize_project BUILDER: Creating Vivado project in memory for part xc7k410tffg900-2 INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.3/data/ip'. BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/x300.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/x300_pcie_int.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/x300_core.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/x300_sfpp_io_core.v BUILDER: Adding VHDL : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/x300_zpu_config.vhd BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/x300_db_fe_core.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/soft_ctrl.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/capture_ddrlvds.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/gen_ddrlvds.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/bus_int.v BUILDER: Adding XDC : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/x300.xdc BUILDER: Adding XDC : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/timing.xdc BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/fifo/axi_demux4.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/fifo/axi_demux8.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/fifo/axi_demux.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/fifo/axi_fifo_2clk.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/fifo/axi_fifo32_to_fifo64.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/fifo/axi_fifo64_to_fifo32.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/fifo/axi_fifo32_to_fifo16.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/fifo/axi_fifo16_to_fifo32.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/fifo/axi_fifo_bram.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/fifo/axi_fifo_cascade.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/fifo/axi_fifo_flop2.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/fifo/axi_fifo_flop.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/fifo/axi_fifo_short.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/fifo/axi_fifo.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/fifo/axi_filter_mux4.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/fifo/axi_loopback.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/fifo/axi_mux4.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/fifo/axi_mux8.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/fifo/axi_mux_select.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/fifo/axi_mux.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/fifo/axi_packet_gate.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/fifo/fifo64_to_axi4lite.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/fifo/shortfifo.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/fifo/axis_fifo_monitor.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/fifo/axis_strm_monitor.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/ad5662_auto_spi.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/arb_qualify_master.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/axi_crossbar.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/axi_crossbar_regport.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/axi_fifo_header.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/axi_forwarding_cam.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/axi_setting_reg.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/axi_slave_mux.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/axi_test_vfifo.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/bin2gray.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/binary_encoder.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/filter_bad_sid.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/gpio_atr_io.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/gpio_atr.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/gray2bin.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/por_gen.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/priority_encoder_one_hot.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/priority_encoder.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/radio_ctrl_proc.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/ram_2port.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/reset_sync.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/s7_icap_wb.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/serial_to_settings.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/setting_reg.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/settings_bus_mux.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/settings_bus_timed_2clk.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/simple_i2c_core.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/simple_spi_core.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/synchronizer_impl.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/synchronizer.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/pulse_synchronizer.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/user_settings.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/axil_regport_master.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/axil_to_ni_regport.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/regport_resp_mux.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/regport_to_xbar_settingsbus.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/regport_to_settingsbus.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/pulse_stretch.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/mdio_master.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/map/cam_priority_encoder.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/map/cam_bram.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/map/cam_srl.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/map/cam.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/map/kv_map.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/map/axis_muxed_kv_map.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/simple_gemac/simple_gemac_wrapper.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/simple_gemac/simple_gemac.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/simple_gemac/simple_gemac_tx.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/simple_gemac/simple_gemac_rx.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/simple_gemac/crc.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/simple_gemac/delay_line.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/simple_gemac/flow_ctrl_tx.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/simple_gemac/flow_ctrl_rx.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/simple_gemac/address_filter.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/simple_gemac/address_filter_promisc.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/simple_gemac/ll8_to_txmac.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/simple_gemac/rxmac_to_ll8.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/simple_gemac/ll8_to_axi64.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/simple_gemac/axi64_to_ll8.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/simple_gemac/gmii_to_axis.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/simple_gemac/mdio.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/timing/time_compare.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/timing/timekeeper.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/timing/pps_generator.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/timing/pps_synchronizer.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/timing/pulse_generator.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/coregen_dsp/hbdec1.v BUILDER: Adding Netlist : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/coregen_dsp/hbdec1.ngc BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/coregen_dsp/hbdec2.v BUILDER: Adding Netlist : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/coregen_dsp/hbdec2.ngc BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/coregen_dsp/hbdec3.v BUILDER: Adding Netlist : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/coregen_dsp/hbdec3.ngc BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/coregen_dsp/hbint1.v BUILDER: Adding Netlist : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/coregen_dsp/hbint1.ngc BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/coregen_dsp/hbint2.v BUILDER: Adding Netlist : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/coregen_dsp/hbint2.ngc BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/coregen_dsp/hbint3.v BUILDER: Adding Netlist : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/coregen_dsp/hbint3.ngc BUILDER: Adding VHDL : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/zpu/zpu_top_pkg.vhd BUILDER: Adding VHDL : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/zpu/zpu_wb_top.vhd BUILDER: Adding VHDL : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/zpu/wishbone/wishbone_pkg.vhd BUILDER: Adding VHDL : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/zpu/wishbone/zpu_system.vhd BUILDER: Adding VHDL : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/zpu/wishbone/zpu_wb_bridge.vhd BUILDER: Adding VHDL : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/zpu/core/zpu_core.vhd BUILDER: Adding VHDL : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/zpu/core/zpupkg.vhd BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/zpu/zpu_bootram.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/wishbone/simple_uart_rx.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/wishbone/simple_uart_tx.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/wishbone/simple_uart.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/wishbone/wb_1master.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/wishbone/settings_bus.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/wishbone/settings_readback.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/wishbone/i2c_master_top.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/wishbone/i2c_master_bit_ctrl.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/wishbone/i2c_master_byte_ctrl.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/wishbone/axi_stream_to_wb.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/xge/rtl/verilog/fault_sm.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/xge/rtl/verilog/generic_fifo.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/xge/rtl/verilog/generic_fifo_ctrl.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/xge/rtl/verilog/generic_mem_xilinx_block.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/xge/rtl/verilog/generic_mem_medium.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/xge/rtl/verilog/generic_mem_small.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/xge/rtl/verilog/meta_sync.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/xge/rtl/verilog/meta_sync_single.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/xge/rtl/verilog/rx_checker.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/xge/rtl/verilog/rx_data_fifo.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/xge/rtl/verilog/rx_dequeue.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/xge/rtl/verilog/rx_enqueue.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/xge/rtl/verilog/rx_hold_fifo.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/xge/rtl/verilog/sync_clk_core.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/xge/rtl/verilog/sync_clk_wb.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/xge/rtl/verilog/sync_clk_xgmii_tx.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/xge/rtl/verilog/tx_checker.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/xge/rtl/verilog/tx_data_fifo.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/xge/rtl/verilog/tx_dequeue.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/xge/rtl/verilog/tx_enqueue.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/xge/rtl/verilog/tx_hold_fifo.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/xge/rtl/verilog/wishbone_if.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/xge/rtl/verilog/xge_mac.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/xge/rtl/verilog/xge_mac_wb.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/xge_interface/axi64_to_xge64.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/xge_interface/axi_count_packets_in_fifo.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/xge_interface/xge64_to_axi64.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/xge_interface/xge_handshake.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/xge_interface/xge_mac_wrapper.v BUILDER: Adding XDC : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/x300_10ge.xdc BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/ten_gige_phy_clk_gen.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/ten_gige_phy.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma_ex/imports/ten_gig_eth_pcs_pma_example_design.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma_ex/imports/ten_gig_eth_pcs_pma_ff_synchronizer_rst2.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma_ex/imports/ten_gig_eth_pcs_pma_gt_common.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma_ex/imports/ten_gig_eth_pcs_pma_shared_clock_and_reset.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma_ex/imports/ten_gig_eth_pcs_pma_support.v BUILDER: Adding IP : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci BUILDER: Adding XDC : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/x300_1ge.xdc BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gige_phy_clk_gen.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gige_phy.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/one_gig_eth_pcs_pma_ex/imports/one_gig_eth_pcs_pma_example_design.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/one_gig_eth_pcs_pma_ex/imports/one_gig_eth_pcs_pma_reset_sync_ex.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/one_gig_eth_pcs_pma_ex/imports/one_gig_eth_pcs_pma_sync_block_ex.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/one_gig_eth_pcs_pma_ex/imports/one_gig_eth_pcs_pma_tx_elastic_buffer.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/one_gig_eth_pcs_pma_ex/imports/one_gig_eth_pcs_pma_clocking.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/one_gig_eth_pcs_pma_ex/imports/one_gig_eth_pcs_pma_gt_common.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/one_gig_eth_pcs_pma_ex/imports/one_gig_eth_pcs_pma_resets.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/one_gig_eth_pcs_pma_ex/imports/one_gig_eth_pcs_pma_support.v BUILDER: Adding IP : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci BUILDER: Adding XDC : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/x300_10ge_port1.xdc BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/io_port2/LvFpga_Chinch_Interface.v BUILDER: Adding Netlist : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/io_port2/LvFpga_Chinch_Interface.ngc BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/io_port2/ioport2_msg_codec.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/io_port2/pcie_pkt_route_specifier.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/io_port2/pcie_axi_wb_conv.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/io_port2/pcie_wb_reg_core.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/io_port2/pcie_iop2_msg_arbiter.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/io_port2/pcie_basic_regs.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/io_port2/pcie_dma_ctrl.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/io_port2/data_swapper_64.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/io_port2/pcie_lossy_samp_gate.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/packet_proc/chdr_eth_framer.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/packet_proc/cvita_chunker.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/packet_proc/cvita_dechunker.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/packet_proc/cvita_dest_lookup.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/packet_proc/cvita_insert_tlast.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/packet_proc/cvita_packet_debug.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/packet_proc/eth_dispatch.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/packet_proc/eth_interface.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/packet_proc/fix_short_packet.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/packet_proc/ip_hdr_checksum.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/packet_proc/source_flow_control.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/packet_proc/vita_eth_framer.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/packet_proc/arm_deframer.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/vita/flow_control_responder.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/vita/packet_error_responder.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/dsp/acc.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/dsp/add2_and_clip_reg.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/dsp/add2_and_clip.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/dsp/add2_and_round_reg.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/dsp/add2_and_round.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/dsp/add2_reg.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/dsp/add2.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/dsp/add_then_mac.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/dsp/cic_decim.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/dsp/cic_dec_shifter.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/dsp/cic_interp.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/dsp/cic_int_shifter.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/dsp/cic_strober.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/dsp/clip_reg.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/dsp/clip.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/dsp/cordic_stage.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/dsp/cordic_z24.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/dsp/ddc_chain.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/dsp/duc_chain.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/dsp/hb47_int.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/dsp/hb_dec.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/dsp/hb_interp.v BUILDER: [WARNING] File ignored!!!: /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/dsp/Makefile.srcs BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/dsp/mult_add_clip.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/dsp/round_reg.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/dsp/round_sd.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/dsp/round.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/dsp/rx_dcoffset.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/dsp/rx_frontend.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/dsp/sign_extend.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/dsp/small_hb_dec.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/dsp/small_hb_int.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/dsp/srl.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/dsp/tx_frontend.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/dsp/variable_delay_line.v BUILDER: Adding IP : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ddr3_32bit/ddr3_32bit.xci BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ddr3_32bit/ddr3_32bit/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v CRITICAL WARNING: [filemgmt 20-1440] File '/home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ddr3_32bit/ddr3_32bit/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v' already exists in the project as a part of sub-design file '/home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ddr3_32bit/ddr3_32bit.xci'. Explicitly adding the file outside the scope of the sub-design can lead to unintended behaviors and is not recommended. BUILDER: Adding XDC : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/x300_dram.xdc BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/axi/axi_chdr_header_trigger.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/axi/axi_chdr_test_pattern.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/axi/axi_defs.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/axi/axi_dma_fifo.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/axi/axi_dma_master.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/axi/axi_replay.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/axi/axi_embed_tlast.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/axi/axi_extract_tlast.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/axi/axi_fast_extract_tlast.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/axi/axi_fast_fifo.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/axi/axi_to_strobed.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/axi/axi_dummy.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/axi/strobed_to_axi.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/axi/axi_add_preamble.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/axi/axi_strip_preamble.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/axi/crc_xnor.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/axi/axis_packet_flush.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/axi/axis_shift_register.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/axi/axis_upsizer.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/axi/axis_downsizer.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/axi/axis_width_conv.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/radio/radio_datapath_core.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/radio/radio_core_regs.vh BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/radio/db_control.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/radio/quarter_rate_downconverter.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/radio/rx_frontend_gen3.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/radio/tx_frontend_gen3.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/radio/rx_control_gen3.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/radio/tx_control_gen3.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/radio/noc_block_radio_core.v BUILDER: Adding VHDL : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/radio/WrapBufg.vhd BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/io_cap_gen/cap_pattern_verifier.v BUILDER: Adding IP : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci BUILDER: Adding IP : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci BUILDER: Adding IP : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/bootram/bootram.xci BUILDER: Adding IP : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/bus_clk_gen/bus_clk_gen.xci BUILDER: Adding IP : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/fifo_4k_2clk/fifo_4k_2clk.xci BUILDER: Adding IP : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/fifo_short_2clk/fifo_short_2clk.xci BUILDER: Adding IP : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/pcie_clk_gen/pcie_clk_gen.xci BUILDER: Adding IP : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/radio_clk_gen/radio_clk_gen.xci BUILDER: Adding Block Design to list (added after IP regeneration): /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd.bd BUILDER: Adding Block Design XML to list (added after IP regeneration): /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd.bxml BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd_wrapper.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/cmd_pkt_proc.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/chdr_fifo_large.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/chdr_framer.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/chdr_framer_2clk.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/chdr_deframer.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/chdr_deframer_2clk.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_shell.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_shell_regs.vh BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/chdr_pkt_types.vh BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/axi_packet_mux.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/axi_wrapper.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/axi_bit_reduce.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_block_axi_fifo_loopback.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_block_axi_dma_fifo.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_block_replay.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_block_fir_filter.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_block_fft.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_block_null_source_sink.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_block_schmidl_cox.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_block_packet_resizer.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_block_sos_filter.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_block_split_stream.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_block_vector_iir.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_block_addsub.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_block_window.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_block_keep_one_in_n.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_block_pfb.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_block_export_io.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_block_conv_encoder_qpsk.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_block_siggen.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_block_digital_gain.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_block_debug.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/pfb.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/pfb_stage.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/null_source.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/schmidl_cox.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/split_stream.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/split_stream_fifo.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/conj.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/delay_fifo.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/delay_type2.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/delay_type3.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/delay_type4.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/complex_to_magsq.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/phase_accum.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/complex_invert.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/periodic_framer.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/threshold_scaled.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/moving_sum.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/peak_finder.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/window.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/counter.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/puncture.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/symbol_to_gray_bits.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/ram_to_fifo.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/const.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/const_sreg.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/cmul.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/cadd.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_input_port.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_output_port.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_responder.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/keep_one_in_n.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/vector_iir.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/addsub.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/packet_resizer.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/axi_pipe.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/multiply.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/mult.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/mult_add.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/mult_rc.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/mult_add_rc.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/fft_shift.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/axi_pipe_join.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/axi_pipe_mac.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/axi_round_and_clip_complex.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/axi_round_complex.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/axi_clip_complex.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/axi_join.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/axi_sync.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/split_complex.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/axi_round_and_clip.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/join_complex.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/axi_round.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/axi_clip.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/axi_clip_unsigned.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/axi_serializer.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/axi_deserializer.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/axi_packer.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/complex_to_mag_approx.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_block_file_source.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/file_source.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/ofdm_plateau_detector.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/ofdm_peak_detector.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/fosphor/delay.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/fosphor/fifo_srl.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/fosphor/rng.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/fosphor/f15_avg.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/fosphor/f15_binmap.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/fosphor/f15_core.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/fosphor/f15_eoseq.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/fosphor/f15_histo_mem.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/fosphor/f15_line_mem.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/fosphor/f15_logpwr.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/fosphor/f15_maxhold.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/fosphor/f15_packetizer.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/fosphor/f15_rise_decay.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/fosphor/f15_wf_agg.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/fosphor/axi_logpwr.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_block_logpwr.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_block_fosphor.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_block_moving_avg.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/ofdm_constellation_demapper.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_block_ofdm_constellation_demapper.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/one_tap_equalizer.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_block_eq.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_block_ddc.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_block_duc.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/cvita_hdr_parser.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/cvita_hdr_encoder.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/cvita_hdr_decoder.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/cvita_hdr_modify.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/axi_async_stream.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/axi_rate_change.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/axi_tag_time.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/axi_drop_partial_packet.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/cordic.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/cordic_timed.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/ddc.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/duc.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/cic_decimate.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/cic_interpolate.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/sine_tone.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/axi_fir_filter.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/fir_filter_slice.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/axi_fir_filter_dec.v BUILDER: Adding VHDL : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/addsub.vhd BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/dds_freq_tune.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/dds_timed.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/datapath_gatekeeper.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/biquad_filter.v BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_traffic_counter.v BUILDER: Adding IP : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_fft/axi_fft.xci BUILDER: Adding IP : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xci BUILDER: Adding IP : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb47/axi_hb47.xci BUILDER: Adding IP : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/complex_to_magphase/complex_to_magphase.xci BUILDER: Adding IP : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/complex_to_magphase_int16_int24/complex_to_magphase_int16_int24.xci BUILDER: Adding IP : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/complex_to_magphase_int32/complex_to_magphase_int32.xci BUILDER: Adding IP : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/complex_multiplier/complex_multiplier.xci BUILDER: Adding IP : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/complex_multiplier_dds/complex_multiplier_dds.xci BUILDER: Adding IP : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/cordic_rotator/cordic_rotator.xci BUILDER: Adding IP : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/cordic_rotator24/cordic_rotator24.xci BUILDER: Adding IP : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/cordic_rotate_int24_int16/cordic_rotate_int24_int16.xci BUILDER: Adding IP : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/cordic_rotate_int24/cordic_rotate_int24.xci BUILDER: Adding IP : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/divide_int16/divide_int16.xci BUILDER: Adding IP : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/divide_int24/divide_int24.xci BUILDER: Adding IP : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/divide_int32/divide_int32.xci BUILDER: Adding IP : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/divide_uint32/divide_uint32.xci BUILDER: Adding IP : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/divide_int16_int32/divide_int16_int32.xci BUILDER: Adding IP : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/dds_sin_cos_lut_only/dds_sin_cos_lut_only.xci BUILDER: Adding Verilog : /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/addsub_hls/solution/impl/verilog/addsub_hls.v BUILDER: Adding file from Block Design list: /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd.bd BUILDER: Adding file from Block Design list: /home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd.bxml BUILDER: Setting x300 as the top module # vivado_utils::synthesize_design BUILDER: Synthesizing design Command: synth_design -top x300 -part xc7k410tffg900-2 -verilog_define BUILD_1G=1 -verilog_define BUILD_10G=1 -verilog_define SFP0_1GBE=1 -verilog_define SFP1_10GBE=1 -verilog_define RFNOC=1 -verilog_define X310=1 -verilog_define GIT_HASH=32'hfff03b00 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t' INFO: [Common 17-86] Your Synthesis license expires in 11 day(s) INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 29534 WARNING: [Synth 8-2611] redeclaration of ansi port ce_clk is not allowed [/home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/rfnoc_ce_auto_inst_x310.v:19] WARNING: [Synth 8-2611] redeclaration of ansi port ce_rst is not allowed [/home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/rfnoc_ce_auto_inst_x310.v:20] WARNING: [Synth 8-976] mac_crit_err_latch has already been declared [/home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/x300_sfpp_io_core.v:416] WARNING: [Synth 8-2654] second declaration of mac_crit_err_latch ignored [/home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/x300_sfpp_io_core.v:416] INFO: [Synth 8-994] mac_crit_err_latch is declared here [/home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/x300_sfpp_io_core.v:362] WARNING: [Synth 8-1849] concatenation with unsized literal; will interpret as 32 bits [/home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/x300_sfpp_io_core.v:429] WARNING: [Synth 8-1849] concatenation with unsized literal; will interpret as 32 bits [/home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/x300_sfpp_io_core.v:430] WARNING: [Synth 8-1849] concatenation with unsized literal; will interpret as 32 bits [/home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/x300_sfpp_io_core.v:431] WARNING: [Synth 8-1849] concatenation with unsized literal; will interpret as 32 bits [/home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/x300_sfpp_io_core.v:432] WARNING: [Synth 8-1849] concatenation with unsized literal; will interpret as 32 bits [/home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/top/x300/x300_sfpp_io_core.v:433] WARNING: [Synth 8-2507] parameter declaration becomes local in axil_regport_master with formal parameter declaration list [/home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/axil_regport_master.v:90] WARNING: [Synth 8-2507] parameter declaration becomes local in cam_priority_encoder with formal parameter declaration list [/home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/map/cam_priority_encoder.v:46] WARNING: [Synth 8-2507] parameter declaration becomes local in cam_priority_encoder with formal parameter declaration list [/home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/map/cam_priority_encoder.v:47] WARNING: [Synth 8-2507] parameter declaration becomes local in axis_muxed_kv_map with formal parameter declaration list [/home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/map/axis_muxed_kv_map.v:32] WARNING: [Synth 8-2507] parameter declaration becomes local in axis_muxed_kv_map with formal parameter declaration list [/home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/control/map/axis_muxed_kv_map.v:33] WARNING: [Synth 8-2306] macro IDLE redefined [/home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/xge/rtl/verilog/rx_checker.v:7] WARNING: [Synth 8-2306] macro IDLE redefined [/home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/xge/rtl/verilog/defines.v:57] WARNING: [Synth 8-2306] macro IDLE redefined [/home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/xge/rtl/verilog/tx_checker.v:6] WARNING: [Synth 8-2306] macro IDLE redefined [/home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/xge/rtl/verilog/defines.v:57] WARNING: [Synth 8-2507] parameter declaration becomes local in variable_delay_line with formal parameter declaration list [/home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/dsp/variable_delay_line.v:47] WARNING: [Synth 8-2611] redeclaration of ansi port sid is not allowed [/home/ck/pybombs-rfnoc/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/file_source.v:38] --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 6566.902 ; gain = 29.629 ; free physical = 117538 ; free virtual = 124018 ---------------------------------------------------------------------------------
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