Hello Cherif and Brian, I did find the clock signal re-definitions you were talking about in *rfnoc_ce_auto_inst_x310.v*, and I did notice that the file is generated by the *uhd_image_builder.py file*, so I looked in the *uhd_image_builder.py* file to find the code that generates *rfnoc_ce_auto_inst_x310.v*. I was able to find the signal re-definitions in the image builder file, lines 43 and 44 I believe, and I changed them there. So far that seems to have fixed the issue and I have successfully been able to build a custom FPGA image. The one thing I have yet to try is building one with a custom RFNoC block. Anyways, thank you for the help and I will post again if I run into any other issues.
Best Regards, Jerrid _______________________________________________ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
