Interesting.
On the Ettus website at: https://files.ettus.com/manual/md_usrp3_build_instructions.html right at the top, they list: Dependencies and Requirements Dependencies The USRP FPGA build system requires a UNIX-like environment with the following dependencies * Xilinx Vivado 2019.1<https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/2019-1.html> (For 7 Series FPGAs) I figured I would try 2019.2. I mean it couldn't be that much different than 2019.1. But, it wouldn't be the first time the web documentation was not correct. I guess I'll back off my version and see where that gets me. Thanks much for the help, Nick! Jeff ________________________________ From: Nick Foster <[email protected]> Sent: Monday, March 16, 2020 2:40 PM To: Jeff S <[email protected]> Cc: [email protected] <[email protected]> Subject: Re: [USRP-users] RFNoC Build Error? Or Something Else? You're using the wrong version of Vivado. You need to use Vivado 2017.4. On Mon, Mar 16, 2020 at 12:38 PM Jeff S via USRP-users <[email protected]<mailto:[email protected]>> wrote: Hi, All. I am trying to start down the path of RFNoC development, and I am following the steps outlined on the following page: https://kb.ettus.com/Getting_Started_with_RFNoC_Development I have already ran into a problem, and I'm not quite sure where to go with it. I'm not sure if I have missed a step somewhere in my installation, or if something else is wrong. I am hoping someone can point me in the correct direction. Here's what I have: $ uhd_config_info --version UHD 4.0.0.rfnoc-devel-702-geec24d7b $ ./uhd_image_builder.py window fft -d x310 -t X310_RFNOC_HG -m 5 --fill-with-fifos --Using the following blocks to generate image: * window * fft Adding CE instantiation file for 'X310_RFNOC_HG' changing temporarily working directory to /home/user/offline/src/fpga/usrp3/tools/scripts/../../top/x300 Setting up a 64-bit FPGA build environment for the USRP-X3x0... - Vivado: Found (/tools/Xilinx/Vivado/2019.2/bin) Environment successfully initialized. make -f Makefile.x300.inc bin NAME=X310_RFNOC_HG ARCH=kintex7 PART_ID=xc7k410t/ffg900/-2 BUILD_1G=1 BUILD_10G=1 SFP0_1GBE=1 SFP1_10GBE=1 RFNOC=1 X310=1 TOP_MODULE=x300 EXTRA_DEFS="BUILD_1G=1 BUILD_10G=1 SFP0_1GBE=1 SFP1_10GBE=1 RFNOC=1 X310=1 " make[1]: Entering directory '/home/user/offline/src/fpga/usrp3/top/x300' BUILDER: Checking tools... * GNU bash, version 4.4.20(1)-release (x86_64-pc-linux-gnu) * Python 2.7.17 * Vivado v2019.2.1 (64-bit) ======================================================== BUILDER: Building IP ten_gig_eth_pcs_pma ======================================================== BUILDER: Staging IP in build directory... BUILDER: Reserving IP location: /home/user/offline/src/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma BUILDER: Retargeting IP to part kintex7/xc7k410t/ffg900/-2... BUILDER: Building IP... [00:00:00] Executing command: vivado -mode batch -source /home/user/offline/src/fpga/usrp3/tools/scripts/viv_generate_ip.tcl -log ten_gig_eth_pcs_pma.log -nojournal WARNING: [IP_Flow 19-2162] IP 'ten_gig_eth_pcs_pma' is locked: CRITICAL WARNING: [filemgmt 20-1366] Unable to reset target(s) for the following file is locked: /home/user/offline/src/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the following file is locked: /home/user/offline/src/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci [00:00:13] Current task: Initialization +++ Current Phase: Starting [00:00:13] Current task: Initialization +++ Current Phase: Finished [00:00:13] Executing Tcl: synth_design -top ten_gig_eth_pcs_pma -part xc7k410tffg900-2 -mode out_of_context [00:00:13] Starting Synthesis Command WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products for Synthesis target. These output products could be required for synthesis, please generate the output products using the generate_target or synth_ip command before running synth_design. WARNING: [IP_Flow 19-2162] IP 'ten_gig_eth_pcs_pma' is locked: ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/home/user/offline/src/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xml' CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/home/user/offline/src/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xml' CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/home/user/offline/src/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xml' CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/home/user/offline/src/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xml' CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/home/user/offline/src/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xml' ERROR: [Vivado 12-398] No designs are open ERROR: [Common 17-69] Command failed: * IP definition '10G Ethernet PCS/PMA (10GBASE-R/KR) (6.0)' for IP 'ten_gig_eth_pcs_pma' (customized with software release 2017.4) has a different revision in the IP Catalog. [00:00:16] Current task: Synthesis +++ Current Phase: Starting [00:00:16] Current task: Synthesis +++ Current Phase: Finished [00:00:16] Process terminated. Status: Failure ======================================================== Warnings: 3 Critical Warnings: 7 Errors: 9 BUILDER: Releasing IP location: /home/user/offline/src/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma /home/user/offline/src/fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/Makefile.inc:41: recipe for target '/home/user/offline/src/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci.out' failed make[1]: *** [/home/user/offline/src/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci.out] Error 1 make[1]: Leaving directory '/home/user/offline/src/fpga/usrp3/top/x300' Makefile:119: recipe for target 'X310_RFNOC_HG' failed make: *** [X310_RFNOC_HG] Error 2 _______________________________________________ USRP-users mailing list [email protected]<mailto:[email protected]> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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