Hi Dario,
I'm not sure why you're getting that error. Your initial command doesn't
look right ("GUI=1 make n310_rfnoc_image_core") but maybe that's just a
typo. Did you perhaps make changes to the clocking or constraints in the
design? I wouldn't expect building with the ILA to cause this problem. You
might consider running "make cleanall" and rebuilding to make sure
everything is in a clean state and builds correctly. You could also try
your steps on an unmodified design to see if you get different behavior.
Here's the process I typically use to insert an ILA in UHD 4.0. Maybe you
can try it and see if it works for you? I start by marking for debug all
the registers I want to see in the ILA by adding (* mark_debug = "true" *)
to them in the Verilog code. To synthesize the design I would run the
following:
# Run rfnoc_image_builder to update the image Verilog, if needed
rfnoc_image_builder -y n310_rfnoc_image_core.yml --generate-only
# Run synthesis only, in the GUI (be sure to use the N310 target you want
if not N310_XG)
make N310_XG GUI=1 SYNTH=1
After synthesis finishes in the Vivado GUI, I use the debug wizard to
insert the ILA and add the signals I want to see (from the Vivado menu,
click Tools -> Setup Debug...). After I finish the steps in the wizard, I
run the following commands in the Tcl console of the GUI to finish place
and route with the ILA (you can just copy and paste these commands all at
once):
opt_design
place_design
route_design
write_debug_probes -force debug_01.ltx
write_bitstream -force debug_01.bit
After that finishes, I use uhd_image_loader to download the debug
bitstream. For example:
# Copy the correct device tree source file to the same location/name as the
# debug bitstream, if it's different from what's already loaded on the N310.
cd ./build/usrp_n310_fpga_XG.dts ./build-N310_XG/debug_01.dts
# Load the FPGA bitstream
uhd_image_loader --args type=n3xx --fpga-path ./build-N310_XG/debug_01.bit
# Run uhd_usrp_probe to make sure everything is up and running
uhd_usrp_probe
After that, you should be able to see the ILA in the Vivado Hardware
Manager. Load the probes file (debug_01.ltx) to see the debug signal names
you added to the ILA.
There are other flows that should also work.
Thanks,
Wade
On Sat, Nov 21, 2020 at 6:21 PM Dario Pennisi via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Hi,
> i am trying to debug my block and to do so i ran
>
> GUI=1 make n310_rfnoc_image_core
>
> this brings up vivado and allows me to synthesize the design and setup
> ILA. when i try fitting and generating bitstream i get the following error:
>
> [DRC PDRC-29] MMCM_adv_ClkFrequency_clkin1: The calculated frequency
> value, 0.000 MHz, of the CLKIN1_PERIOD attribute on the MMCME2_ADV site
> MMCME2_ADV_X0Y0 (cell n3xx_clocking_i/misc_clock_gen_i/inst/mmcm_adv_inst)
> is outside the allowed range (10.000 - 933.000 MHz). Please change the
> CLKIN1_PERIOD attribute value in order to be within the allowed range for
> this device.
> [DRC PDRC-29] MMCM_adv_ClkFrequency_clkin1: The calculated frequency
> value, 0.000 MHz, of the CLKIN1_PERIOD attribute on the MMCME2_ADV site
> MMCME2_ADV_X1Y5 (cell
> u_ddr3_32bit/u_ddr3_32bit_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i) is
> outside the allowed range (10.000 - 933.000 MHz). Please change the
> CLKIN1_PERIOD attribute value in order to be within the allowed range for
> this device.
> [DRC PDRC-38] PLL_adv_ClkFrequency_clkin1: The calculated frequency value,
> 0.000 MHz, of the CLKIN1_PERIOD attribute on the PLLE2_ADV site
> PLLE2_ADV_X1Y5 (cell
> u_ddr3_32bit/u_ddr3_32bit_mig/u_ddr3_infrastructure/plle2_i) is outside the
> allowed range (19.000 - 933.000 MHz). Please change the CLKIN1_PERIOD
> attribute value in order to be within the allowed range for this device.
>
> strange enough i don't get these when running from console.
> any suggestions?
>
> Dario Pennisi
>
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