Dear all,
I have an issue with a testbench for a custom RFNoC block.
The testbench template is taken from host/example/rfnoc-example
and generated with rfnoc_create_verilog.py,
as stated in the wiki [1].
Running "make testbenches" completes without issue.
However, running the testbench with GUI ("make testbenches GUI=1")
failed with "FATAL_ERROR: Vivado Simulator kernel has discovered
an exceptional condition from which it cannot recover" during the wave
generation (1%), making the soft unusable.
Files: Block [2], testbench [3], log [4].
Version: UHD 4.0, Vivado 2019.1.
I would like to simulate signal waveforms to check latency/timing.
Any idea how to fix or to check latency/timing?
[1]
https://kb.ettus.com/Getting_Started_with_RFNoC_in_UHD_4.0#Generating_Your_Block_Using_the_ModTool
[2] https://paste.debian.net/hidden/5fa3b59e/
[3] https://paste.debian.net/hidden/281ffb17/
[4] https://paste.debian.net/hidden/db686780/
Regards
--
Cédric Hannotier
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