Hello, I am working on a E320 USRP unit and using UHD-4.1.0.5. I prepared my own FPGA image that has 1 radio block and 1 replay block with 2 ports (channels) I would like to be able to simultaneously perform playback of 1 Tx channel and recording of 2 Rx channels (to/from different memory locations) The example rfnoc_replay_samples_from_file.cpp is only helpful to some extent because it shows only the playback path and I am having some difficulty setting up the recording path.
I have a few questions about the replay block functionality and connectivity that I hope you may be able to resolve. 1. Is the replay block bi-directional? If I have a replay block with 1 channel, can it be used for both playback of samples and recording of samples (from/to different memory locations) simultaneously ? or does each operation require one channel? 2. If the answer to question (1) is no then I guess I need at least 3 replay channels. Is it possible to define in the FPGA image (in the yml file) a replay block with 3 channels (ports) or does it have to be a power of 2? a multiple of 2? I didn't want to try and see what happens because it takes a while to compile the FPGA image and I would rather get it right on the 1st try. 3. I would like to issue samples recording at a predetermined time for a fixed size data chunk and then at my own leisure dump the memory buffer that was recorded to a file. Since I don't have a working example I am having some difficulty getting it right. a. The graph should be Radio --> Replay --> rx_stream. Is this correct? b. I should start my recording with replay_ctrl->record_restart and check for fullness, right? c. Then how do I get the rx_stream to dump it to file? Do I need to do playback for this to happen, mirroring what is going on in the rfnoc_replay_samples_from_file example? If someone has a working code snippet I would appreciate it if they can share it. Thanks, Ofer Saferman -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.
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