Hi, You should not expect that integrate or add Xilinx IP core directly to
RFNOC blocks, Even If you be a master in Verilog...
If you see the UHD source code you will realize that UHD is an RFNOC
framework for USRP ...
For working with the RFNOC UHD framework you should know more details:
1)Please see this link
https://files.ettus.com/app_notes/RFNoC_Specification.pdf
2)Any RFNOC block has two files, noc_shell_blockname.v and
rfnoc_block_blockname.v these two file are very important
the first file is a low-level definition for the RFNOC block and the second
file is the high-level definition for the block. I mention that we should
use IP core in the second file ...
And more details that you should study UHD source code till getting them...
On Fri, Jun 3, 2022 at 6:03 PM Rob Kossler <rkoss...@nd.edu> wrote:
> Hi Maria,
> I apologize but I am not very experienced with these matters. I am able to
> copy the rfnoc-example folder to an OOT location and build it and I know it
> has both OOT and in-tree IP options. In the past I have successfully run
> the 'make <testbench>' and also built an image such as "make <x300_core>".
> But, outside of that, I don't really know what I'm doing....
> Rob
>
> On Fri, Jun 3, 2022 at 9:05 AM Maria Muñoz <mamuk...@gmail.com> wrote:
>
>> Hi Rob,
>>
>> I try to put these lines in the makefile.srcs inside my_block/fpga folder
>> as in the rfnoc example:
>>
>> #RFNOC_OOT_SRCS += $(abspath $(addprefix ${RFNOC_EXAMPLE_DIR},
>> #my_other_module.v \
>> #ip/my_ip_core/my_ip_core.xci \
>> #))
>>
>> I add my .xci IP to this folder and give the name of the IP as a
>> rfnoc_oot_src. I can compile the block but when I try to perform synthesis
>> it gives me this error:
>>
>> ERROR: [DRC INBB-3] Black Box Instances: Cell
>> 'x300_core/bus_int_i/rfnoc_sandbox_i/b_3/top_i/my_clk' of type 'clk_wiz_0'
>> has undefined contents and is considered a black box. The contents of this
>> cell must be defined for opt_design to complete successfully.
>> ERROR: [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run.
>> ERROR: [Common 17-39] 'opt_design' failed due to earlier errors.
>>
>> So I think I am missing something. I do not see anything else related to
>> IP core. Is there something else I have to do?
>>
>> Kind regards,
>> Maria
>>
>> El mié, 1 jun 2022 a las 17:48, Rob Kossler (<rkoss...@nd.edu>) escribió:
>>
>>> Hi Maria,
>>> The rfnoc-example folder within the UHD tree shows an example of how to
>>> add an out-of-tree IP block. Did you look at this yet?
>>> Rob
>>>
>>> On Wed, Jun 1, 2022 at 5:12 AM Maria Muñoz <mamuk...@gmail.com> wrote:
>>>
>>>> Hi all,
>>>>
>>>> I'm trying to synthesize a design that includes a vivado ip core
>>>> inside.
>>>> Normally, I add my .vhd/.v source files to the Makefile.srcs inside my
>>>> block like this:
>>>>
>>>> RFNOC_OOT_SRCS += $(addprefix $(dir $(abspath $(lastword
>>>> $(MAKEFILE_LIST)))), \
>>>> source1.vhd \
>>>> source2.v \
>>>> source3.v \
>>>> )
>>>>
>>>> But adding the .xci file of my IP core does not work.
>>>>
>>>> What is the process to include this file in the makefile chain to
>>>> compile it?
>>>>
>>>> Kind Regards,
>>>>
>>>> Maria.
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>>>>
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