Thank you very much! You were right. I made a mistake with the clock in my module.
El mié, 28 sept 2022 a las 4:19, Wade Fife (<wade.f...@ettus.com>) escribió: > There's not enough information in the screen shot, but I think the output > of the double synchronizer is on a different clock domain than flop flop > (dato_entrada) being reset by it. > > The reset signal needs to be driven by the same clock as the flip flop > being reset, otherwise Vivado can't ensure that the requirements of the FF > will be met, resulting in this timing violation. > > Make sure you're using the right clock and reset signal for your > dato_entrada register. > > Wade > > On Tue, Sep 27, 2022 at 9:10 AM Brian Padalino <bpadal...@gmail.com> > wrote: > >> On Tue, Sep 27, 2022 at 7:21 AM <adri96r...@gmail.com> wrote: >> >>> Hi every one! >>> >>> >>> I am facing some problems with reset timing violations. This is is one >>> for example, and i have a fews. I tried to instantiate the reset signal but >>> it didn work. I don know how to fix it. On the other side, i have seen a >>> reset generation in a noc shell and i was wondering if i have to generate a >>> new one from a previous one. >>> >> I can't see much other than the names of the signals and the negative >> slack, but the hierarchy seems to indicate it's part of a synchronizer >> that's been double flopped, so maybe there should be a false path >> associated with it in your constraints? >> >> Brian >> _______________________________________________ >> USRP-users mailing list -- usrp-users@lists.ettus.com >> To unsubscribe send an email to usrp-users-le...@lists.ettus.com >> >
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