Why initialize large array in Verilog is not successfully. When size of
array is 255 it work like charm but for other number more than 255 like
1024 and ....
we observe all array is filled with zero? why large array in FPGA can not
initailize correctly????
Code:
reg signed [15:0] data_i_pattern_buffer [1024:0];
reg signed [15:0] data_q_pattern_buffer [1024:0];
$readmemh("out_i.txt",data_i_pattern_buffer,0,1024);
$readmemh("out_q.txt",data_q_pattern_buffer,0,1024);
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