Hi all, I am using UHD 4.0 in an E320 USRP. I would like to use the axi_ram_fifo block to communicate with the DMA, but I have some doubts about it. I notice that the maximum width I can test is 64, if I try 128 or 256 it fails. The io_signatures.yml file has this line:
Axi_ram: Type: axi4_mm_4x64_4g Does this mean it only supports 64-bit width? Is there any way to increase the width? Kind Regards, Maria
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