Hi Wade, Thanks for the answer and sorry for the late reply.
I had seen that UHD 4.3 has this line in the io_signatures.yml (axi_4mm part): "# AXI4 memory-mapped interface (up to 4 x 512-bit data and 48-bit address)" So that's why I had asked if more than 64-bit width was possible. Anyway, 64-bits is okay for my application. Thanks again! Kind regards, Maria. El vie, 21 oct 2022 a las 19:28, Wade Fife (<wade.f...@ettus.com>) escribió: > Right, it needs to be 64 bits to work without other changes. That's the > width of the AXI Interconnect to which the axi_ram block connects. However, > the connection to the DRAM is 256 bits. That gets shared across 4 ports by > the AXI Interconnect, and each port could potentially be reading and > writing simultaneously. This is why the default is to provide four 64-bit > ports. > > It would be unusual to need more than 64 bits per port, since you're > limited to 64-bits per port by RFNoC on E320. However, you could make it > wider if you modify the AXI Interconnect appropriately and update the IO > signatures. > > > https://github.com/EttusResearch/uhddev/tree/UHD-4.0/fpga/usrp3/top/e320/ip/axi_intercon_4x64_256_bd > > https://github.com/EttusResearch/uhddev/blob/UHD-4.0/fpga/usrp3/top/e320/e320_core.v#L610 > > Wade > > On Thu, Oct 20, 2022 at 5:27 AM Maria Muñoz <mamuk...@gmail.com> wrote: > >> Hi all, >> >> I am using UHD 4.0 in an E320 USRP. >> I would like to use the axi_ram_fifo block to communicate with the DMA, >> but I have some doubts about it. >> I notice that the maximum width I can test is 64, if I try 128 or 256 it >> fails. The io_signatures.yml file has this line: >> >> Axi_ram: >> Type: axi4_mm_4x64_4g >> >> Does this mean it only supports 64-bit width? Is there any way to >> increase the width? >> >> Kind Regards, >> Maria >> _______________________________________________ >> USRP-users mailing list -- usrp-users@lists.ettus.com >> To unsubscribe send an email to usrp-users-le...@lists.ettus.com >> >
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