Dear Rob,
Sorry for the wrong command. I executed following command “uhd_image_loader
--args type=e3xx,adr=192.168.10.2
--fpga-path=/home/grcusrp/uhd/fpga/usrp3/top/e31x/build/usrp_e310_sg3_fpga.bit”.
Please also find the attached YML file.
# General parameters
# -----------------------------------------
schema: rfnoc_imagebuilder_args # Identifier for the schema used to
validate this file
copyright: >- # Copyright information used in file
headers
Copyright 2023 Ettus Research, a National Instruments Brand
license: >- # License information used in file
headers
SPDX-License-Identifier: LGPL-3.0-or-later
version: '1.0' # File version
chdr_width: 64 # Bit width of the CHDR bus for this
image
device: 'e310' # USRP type
image_core_name: 'e310' # Name to use for the RFNoC Image Core
files
default_target: 'DRAM=1 E310_SG3'
# A list of all stream endpoints in design
# ----------------------------------------
stream_endpoints:
ep0: # Stream endpoint name
ctrl: True # Endpoint passes control traffic
data: True # Endpoint passes data traffic
buff_size: 4096 # Ingress buffer size for data
ep1:
ctrl: False
data: True
buff_size: 4096
ep2:
ctrl: False
data: True
buff_size: 4096
ep3:
ctrl: False
data: True
buff_size: 4096
# A list of all NoC blocks in design
# ----------------------------------
noc_blocks:
radio0: # NoC block name
block_desc: 'radio.yml' # Block device descriptor
parameters:
NUM_PORTS: 2
replay0:
block_desc: 'replay.yml'
parameters:
NUM_PORTS: 2
MEM_DATA_W: 64
MEM_ADDR_W: 30
# A list of all static connections in design
# ------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the
following keys
# - srcblk = Source block to connect
# - srcport = Port on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Port on the destination block to connect
connections:
# TX A
- { srcblk: ep0, srcport: out0, dstblk: radio0, dstport: in_0 }
# RX A
- { srcblk: radio0, srcport: out_0, dstblk: ep0, dstport: in0 }
# TX B
- { srcblk: ep1, srcport: out0, dstblk: radio0, dstport: in_1 }
# RX B
- { srcblk: radio0, srcport: out_1, dstblk: ep1, dstport: in0 }
#
# Replay Connections
- { srcblk: ep2, srcport: out0, dstblk: replay0, dstport: in_0 }
- { srcblk: replay0, srcport: out_0, dstblk: ep2, dstport: in0 }
- { srcblk: ep3, srcport: out0, dstblk: replay0, dstport: in_1 }
- { srcblk: replay0, srcport: out_1, dstblk: ep3, dstport: in0 }
# BSP Connections
- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport }
- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time }
# A list of all clock domain connections in design
# ------------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the
following keys
# - srcblk = Source block to connect (Always "_device"_)
# - srcport = Clock domain on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Clock domain on the destination block to connect
clk_domains:
- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
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