Hi Muhammad, Originally, you had some build errors such that the design "didn't fit" on the FPGA. How did you fix these? From previous experience, I discovered that it was necessary to use the option DRAM=1 when building the E31x with the Replay block. I see that in your YML, this option is included in the "default target" but I am wondering if it was not used on your specific build because you specified the option "-t E310_SG3". Perhaps if you rebuild without specifying the target option it will use the default which will include DRAM=1.
But, even if you successfully attempt the build with the DRAM=1 option, there is a reasonable chance that the build will fail because the design may be too big for the FPGA. In this case, you may want to build with "static linking" as in the YML file that I previously sent. Rob On Mon, Dec 18, 2023 at 1:13 PM <engr.muhd.has...@gmail.com> wrote: > Dear Rob, > > > I have following bit files generated at the same time. > > 1. > > named “usrp_e310_sg3_fpga.bit”. this file is in build folder > 2. > > named “e31x.bit”. which is in “build-E310_SG3” > > build-E310_SG3 folder and build folder, both are in e31x folder. > > > I tried to run both these files and get same error. > > the commands are. 1. uhd_image_loader --args type=e3xx,adr=192.168.10.2 > --fpga-path=/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-E310_SG3/e31x.bit > > > > 1. > > uhd_image_loader --args type=e3xx,adr=192.168.10.2 > > --fpga-path=/home/grcusrp/uhd/fpga/usrp3/top/e31x/build/usrp_e310_sg3_fpga.bit > > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-le...@lists.ettus.com >
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