Hi Juan,
your question comes just at the right time - we were working on exactly this
feature (front-panel access from custom RFNoC blocks - for **all** RFNoC
enabled devices) recently. The necessary changes are now available in uhd
master and were not yet published as an official UHD release (latest UHD
release at the time of writing, mid January 2026: UHD 4.9.0.1).
What you need is the following:
1. Build and Install UHD
* Build UHD from source using uhd master; install UHD (as long as there is
no new official UHD release after UHD 4.9.0.1)
2. Prepare your RFNoC block
* Write your own RFNoC block. For writing the block as an out-of-tree block,
use the “rfnoc_modtool” utility. It now offers an interactive dialogue for
creating new RFNoC blocks.
* your RFNoC block .yml file (e.g. my_gpio_block.yml) needs to have an IO
port of type “gpio”:\
parameters:\
GPIO_WIDTH: ${ config.device.parameters\['FP_GPIO_BANK_WIDTH'\] }\
(…)\
io_ports:\
gpio:\
type: gpio\
drive: master\
parameters:\
width: "${parameters\['GPIO_WIDTH'\]}"
* Your RFNoC block implementation in Verilog (e.g.
rfnoc_block_my_gpio_block.v) needs these additional signals:\
// GPIO interface\
output wire \[GPIO_WIDTH-1:0\] gpio_out,\
output wire \[GPIO_WIDTH-1:0\] gpio_ddr,\
input wire \[GPIO_WIDTH-1:0\] gpio_in
* In your RFNoC block implementation in Verilog (e.g.
rfnoc_block_my_gpio_block.v), set gpio_ddr\[i\] to 1 if you want GPIO pin i to
be output. Set gpio_out\[i\] to 1 if you want to drive the GPIO pin i high.
gpio_in\[i\] is the input value.
* Your RFNoC image core .yml file (e.g.
n310_rfnoc_image_core_with_my_gpio.yml) needs to instantiate the new block.
Connect the “gpio” port of your block (e.g. “my_gpio_block0”) to the fp_gpio
port of the device:\
noc_blocks:\
(…)\
my_gpio_block0:\
block_desc: 'my_gpio_block.yml'\
connections:\
(…)\
# BSP connections\
(…)\
- { srcblk: my_gpio_block0, srcport: gpio, dstblk: _device_,
dstport: fp_gpio }
3. Build the FPGA
* Use rfnoc_image_builder to build the FPGA from your image core file (e.g.
rfnoc_image_core -y n310_rfnoc_image_core_with_my_gpio.yml (…) )
4. Embedded filesystem on the N310 :
* Use UHD 4.9.0.0/4.9.0.1 filesystem (as long there is no new UHD release
after UHD 4.9.0.1)
* apply the following patch on the device (below
/usr/lib/python3.10/site-packages/usrp_mpm):
https://github.com/EttusResearch/uhd/commit/d7a5dba76e261e111c1b0169654b0ce956a4673e
(as long there is no new UHD release after UHD 4.9.0.1)
* after applying patch, either reboot or execute “systemctl restart usrp-hwd”
5. Write and run your host application
* The host application needs to set the GPIO source for the desired GPIO
pins to “USER_APP” (which stands for: the GPIO pin is controlled by user logic).
* Use the API functions uhd::usrp::multi_usrp::set_gpio_src \[1\] or
uhd::rfnoc::mb_controller::set_gpio_src \[2\] for this.
* Example for using the multi-USRP API from Python:\
usrp = uhd.usrp.MultiUSRP("addr=192.168.10.2") # replace with the actual
IP address of your N310\
usrp.get_gpio_src_banks() # this returns \['FP0'\]\
usrp.get_gpio_src(“FP0”) # this returns \['RF0', 'RF0', 'RF0', 'RF0',
'RF0', 'RF0', 'RF0', 'RF0', 'RF0', 'RF0', 'RF0', 'RF0'\] in case the sources
were not modified after UHD session initialization\
n = 1\
m = 11\
usrp.set_gpio_src(“FP0”, \[“USER_APP”\]\*n + \[“RF0”\]\*m) # use RFNoC as
source for the first n GPIO pins, use the GPIO ATR states for the other m GPIO
pins.\
usrp.get_gpio_src(“FP0”) # this should return the desired GPIO sources
* After the GPIO source was set to “USER_APP” for the desired pin, the
physical value of this pin will be determined by the logic which you have
defined in your RFNoC block (e.g. rfnoc_block_my_gpio_block.v). **Please**
**double check** that you are not driving pins from two sources (e.g. for the
pins that you defined as output in the FPGA, don’t connect circuitry to the
GPIO pins which drives the wire).
Please let me know if you were successful in using the new front-panel GPIO
from RFNoC feature. If not, feel free to ask additional questions.
Kind regards,\
Jörg
\[1\]
https://uhd.readthedocs.io/en/latest/classuhd_1_1usrp_1_1multi__usrp.html#a50538e29e9b2053fe303dfc9dd3a217b\
\[2\]
https://uhd.readthedocs.io/en/latest/classuhd_1_1rfnoc_1_1mb__controller.html#ad278664eb8b74f9695237393553897bd
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