Hi Nico,
I've been having a poke around using a toy wasm example. I'm trying to
understand how the wasm optimization pipeline works. I have this basic
block:
BLOCK B7 <- B4
26: Constant()[word32: 50]
27: Equal(#3, #26)[Word32]
28: Constant()[word32: 0]
29: Equal(#27, #28)[Word32]
30: Branch(#29)[B10, B8, None]
And I can see that MachineOptimizationReducer changes the branch (29)
condition, but it doesn't remove (28) and (27):
BLOCK B6 <- B4
25: Constant()[word32: 50]
26: Equal(#3, #25)[Word32]
27: Constant()[word32: 0]
28: Equal(#26, #27)[Word32]
29: Branch(#26)[B7, B8, None]
I've tried adding DeadCodeElimination, but it always seems to run *before*
MachineOptimizationReducer,
how can I get it to run afterwards?
What I find somewhat worrying is that this IR is lowered to equivalent
looking Turbofan IR but then ISel appears to be using Word32Equal (28) as
the branch condition again:
--- BLOCK B5 id7 <- B4 ---
24: IfFalse(22)
25: Int32Constant[50]
26: Word32Equal(4, 25)
27: Int32Constant[0]
28: Word32Equal(26, 27)
29: Branch[Unspecified, None](26) -> B7, B6
B5: AO#4 (no frame) instructions: [11, 13)
predecessors: B4
11: gap () ()
v7(R) = Arm64Cmp32 && set if equal v0(R) #50
12: gap () ()
Arm64CompareAndBranch32 && branch if not equal v7(R)
[rpo_immediate:7] [rpo_immediate:6]
Any idea of what's going here?
cheers!
On Tuesday, July 25, 2023 at 10:53:01 AM UTC+1 Sam Parker-Haynes wrote:
> Great, thanks for the info, I'll take a look around.
>
> On Tuesday, July 25, 2023 at 10:47:07 AM UTC+1 Nico Hartmann wrote:
>
>> There is not a lot of (up to date) documentation. A very brief summary:
>>
>> The new IR's operations (which replace Turbofan's nodes) are defined in
>> turboshaft/operations.h
>> <https://source.chromium.org/chromium/chromium/src/+/main:v8/src/compiler/turboshaft/operations.h>
>> .
>> The current state of the pipeline is as follows: We run
>> Turbofan's frontend and then translate to the Turboshaft IR (in
>> turboshaft/graph-builder.cc
>> <https://source.chromium.org/chromium/chromium/src/+/main:v8/src/compiler/turboshaft/graph-builder.cc>).
>>
>> Next, the Turboshaft optimization and lowering phases run on the CFG (see
>> primarily pipeline.cc
>> <https://source.chromium.org/chromium/chromium/src/+/main:v8/src/compiler/pipeline.cc>
>> and
>> the turboshaft/*-phase.h included from there). Eventually, we translate the
>> CFG back into Turbofan's sea-of-nodes IR (in
>> turboshaft/recreate-schedule.cc
>> <https://source.chromium.org/chromium/chromium/src/+/main:v8/src/compiler/turboshaft/recreate-schedule.cc>)
>>
>> to run the backend.
>>
>> We are currently working on reimplementing the rest of Turbofan's phases
>> to have a full Turboshaft CFG pipeline eventually, but we plan to ship a
>> first version of Turboshaft soonish, which still only covers part of the
>> pipeline and relies on the translation back and forth.
>>
>> On Tue, Jul 25, 2023 at 11:05 AM Sam Parker-Haynes <sam.p...@arm.com>
>> wrote:
>>
>>> Hi Nico,
>>>
>>> A CFG IR sounds good to me :) I've been hesitate to look as I didn't
>>> know the status, is there any documentation? Is it currently piggybacking
>>> off turbofan for some functionality? I can't immediately see where/how
>>> graph nodes are defined.
>>>
>>> cheers,
>>>
>>> On Tuesday, July 25, 2023 at 9:37:26 AM UTC+1 Nico Hartmann wrote:
>>>
>>>> Hi Sam,
>>>>
>>>> We are currently migrating Turbofan to a new CFG-based IR (Turboshaft).
>>>> This could help.
>>>>
>>>> Cheers,
>>>> Nico
>>>>
>>>> On Tue, Jul 25, 2023 at 10:23 AM Sam Parker-Haynes <sam.p...@arm.com>
>>>> wrote:
>>>>
>>>>> Hi,
>>>>>
>>>>> I've been wondering how to go about adding general support for
>>>>> conditional operations in Turbofan, specifically conditional compares for
>>>>> AArch64. But I now see that Intel APX extensions also support more
>>>>> conditional instructions, beyond cmov.
>>>>>
>>>>> I'm not a huge fan of flag continuations, as it's been too easy for me
>>>>> to introduce bugs while using them, so is there a safer way to approach
>>>>> this?
>>>>>
>>>>> Machine-level predication would seem to require a CFG in a form that
>>>>> isn't really available until during/after jump-threading. So a few
>>>>> questions about jump threading:
>>>>> - Could predication happen there?
>>>>> - Why does jump threading run so late, why not before regalloc?
>>>>>
>>>>> And, in general, what is the policy on having optimisation passes that
>>>>> run on machine code?
>>>>>
>>>>> Thanks,
>>>>> Sam
>>>>>
>>>>> --
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>>>>> .
>>>>>
>>>>
>>>>
>>>> --
>>>> Nico Hartmann | Software Engineer | nicoha...@google.com | Chrome - V8
>>>>
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>>>
>>
>>
>> --
>> Nico Hartmann | Software Engineer | nicoha...@google.com | Chrome - V8
>>
>
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