Den 6. maj 2010 16.42 skrev Søren Gjesse <[email protected]>: > Can the -DCAN_USE_UNALIGNED_ACCESSES=1 part of > > 'CCFLAGS': ['-m32', '-DCAN_USE_UNALIGNED_ACCESSES=1'], > > go into a CPPDEFINS like this > > 'CPPDEFINES': ['CAN_USE_UNALIGNED_ACCESSES'] >
Yes, that would have been better. > > instead? > > Also regarding the comments and the flags to the Android build, why does it > need to be set to 1, isn't it enough to just define it like > > -DCAN_USE_UNALIGNED_ACCESSES > I think we generally set to 1 so that people can write #if or #ifdef. > > Also should we have a --enable-unaligned-access > (and --noenable-unaligned-access)? > Can't do that because the runtime code gets compiled differently, not just the generated code. > > /Søren > > On Thu, May 6, 2010 at 20:49, <[email protected]> wrote: > >> Revision: 4604 >> Author: [email protected] >> Date: Thu May 6 05:49:12 2010 >> Log: Allow unaligned memory accesses on ARM targets that support it. >> The build process must add -DCAN_USE_UNALIGNED_ACCESSES=1 to the >> C++ flags to activate the support. This is a commit for >> Subrato of CodeAurora. See http://codereview.chromium.org/1731013 >> Small edits by Erik Corry to activate unaligned accesses by >> default on the simulator and testing Android builds. >> >> http://code.google.com/p/v8/source/detail?r=4604 >> >> Modified: >> /branches/bleeding_edge/SConstruct >> /branches/bleeding_edge/src/arm/constants-arm.h >> /branches/bleeding_edge/src/arm/regexp-macro-assembler-arm.cc >> /branches/bleeding_edge/src/arm/simulator-arm.cc >> /branches/bleeding_edge/src/globals.h >> >> ======================================= >> --- /branches/bleeding_edge/SConstruct Mon Apr 19 12:30:11 2010 >> +++ /branches/bleeding_edge/SConstruct Thu May 6 05:49:12 2010 >> @@ -84,6 +84,7 @@ >> '-finline-limit=64', >> '-DCAN_USE_VFP_INSTRUCTIONS=1', >> '-DCAN_USE_ARMV7_INSTRUCTIONS=1', >> + '-DCAN_USE_UNALIGNED_ACCESSES=1', >> '-MD'] >> >> ANDROID_INCLUDES = [ANDROID_TOP + '/bionic/libc/arch-arm/include', >> @@ -203,7 +204,7 @@ >> 'CPPDEFINES': ['V8_TARGET_ARCH_ARM'] >> }, >> 'simulator:arm': { >> - 'CCFLAGS': ['-m32'], >> + 'CCFLAGS': ['-m32', '-DCAN_USE_UNALIGNED_ACCESSES=1'], >> 'LINKFLAGS': ['-m32'] >> }, >> 'armvariant:thumb2': { >> ======================================= >> --- /branches/bleeding_edge/src/arm/constants-arm.h Thu Apr 8 >> 06:30:48 2010 >> +++ /branches/bleeding_edge/src/arm/constants-arm.h Thu May 6 >> 05:49:12 2010 >> @@ -72,6 +72,10 @@ >> # define CAN_USE_THUMB_INSTRUCTIONS 1 >> #endif >> >> +#if CAN_USE_UNALIGNED_ACCESSES >> +#define V8_TARGET_CAN_READ_UNALIGNED 1 >> +#endif >> + >> // Using blx may yield better code, so use it when required or when >> available >> #if defined(USE_THUMB_INTERWORK) || defined(CAN_USE_ARMV5_INSTRUCTIONS) >> #define USE_BLX 1 >> ======================================= >> --- /branches/bleeding_edge/src/arm/regexp-macro-assembler-arm.cc >> Mon Apr 19 12:30:11 2010 >> +++ /branches/bleeding_edge/src/arm/regexp-macro-assembler-arm.cc >> Thu May 6 05:49:12 2010 >> @@ -1210,14 +1210,31 @@ >> __ add(r0, current_input_offset(), Operand(cp_offset * char_size())); >> offset = r0; >> } >> - // We assume that we cannot do unaligned loads on ARM, so this function >> - // must only be used to load a single character at a time. >> + // The ldr, str, ldrh, strh instructions can do unaligned accesses, if >> the CPU >> + // and the operating system running on the target allow it. >> + // If unaligned load/stores are not supported then this function must >> only >> + // be used to load a single character at a time. >> +#if !V8_TARGET_CAN_READ_UNALIGNED >> ASSERT(characters == 1); >> +#endif >> + >> if (mode_ == ASCII) { >> - __ ldrb(current_character(), MemOperand(end_of_input_address(), >> offset)); >> + if (characters == 4) { >> + __ ldr(current_character(), MemOperand(end_of_input_address(), >> offset)); >> + } else if (characters == 2) { >> + __ ldrh(current_character(), MemOperand(end_of_input_address(), >> offset)); >> + } else { >> + ASSERT(characters == 1); >> + __ ldrb(current_character(), MemOperand(end_of_input_address(), >> offset)); >> + } >> } else { >> ASSERT(mode_ == UC16); >> - __ ldrh(current_character(), MemOperand(end_of_input_address(), >> offset)); >> + if (characters == 2) { >> + __ ldr(current_character(), MemOperand(end_of_input_address(), >> offset)); >> + } else { >> + ASSERT(characters == 1); >> + __ ldrh(current_character(), MemOperand(end_of_input_address(), >> offset)); >> + } >> } >> } >> >> ======================================= >> --- /branches/bleeding_edge/src/arm/simulator-arm.cc Wed Apr 28 >> 00:15:34 2010 >> +++ /branches/bleeding_edge/src/arm/simulator-arm.cc Thu May 6 >> 05:49:12 2010 >> @@ -864,16 +864,25 @@ >> registers_[12] = 0x50Bad4U; >> } >> >> - >> -// The ARM cannot do unaligned reads and writes. On some ARM platforms >> an >> -// interrupt is caused. On others it does a funky rotation thing. For >> now we >> -// simply disallow unaligned reads, but at some point we may want to move >> to >> -// emulating the rotate behaviour. Note that simulator runs have the >> runtime >> +// Some Operating Systems allow unaligned access on ARMv7 targets. We >> +// assume that unaligned accesses are not allowed unless the v8 build >> system >> +// defines the CAN_USE_UNALIGNED_ACCESSES macro to be non-zero. >> +// The following statements below describes the behavior of the ARM CPUs >> +// that don't support unaligned access. >> +// Some ARM platforms raise an interrupt on detecting unaligned access. >> +// On others it does a funky rotation thing. For now we >> +// simply disallow unaligned reads. Note that simulator runs have the >> runtime >> // system running directly on the host system and only generated code is >> // executed in the simulator. Since the host is typically IA32 we will >> not >> -// get the correct ARM-like behaviour on unaligned accesses. >> +// get the correct ARM-like behaviour on unaligned accesses for those ARM >> +// targets that don't support unaligned loads and stores. >> + >> >> int Simulator::ReadW(int32_t addr, Instr* instr) { >> +#if V8_TARGET_CAN_READ_UNALIGNED >> + intptr_t* ptr = reinterpret_cast<intptr_t*>(addr); >> + return *ptr; >> +#else >> if ((addr & 3) == 0) { >> intptr_t* ptr = reinterpret_cast<intptr_t*>(addr); >> return *ptr; >> @@ -881,10 +890,16 @@ >> PrintF("Unaligned read at 0x%08x\n", addr); >> UNIMPLEMENTED(); >> return 0; >> +#endif >> } >> >> >> void Simulator::WriteW(int32_t addr, int value, Instr* instr) { >> +#if V8_TARGET_CAN_READ_UNALIGNED >> + intptr_t* ptr = reinterpret_cast<intptr_t*>(addr); >> + *ptr = value; >> + return; >> +#else >> if ((addr & 3) == 0) { >> intptr_t* ptr = reinterpret_cast<intptr_t*>(addr); >> *ptr = value; >> @@ -892,10 +907,15 @@ >> } >> PrintF("Unaligned write at 0x%08x, pc=%p\n", addr, instr); >> UNIMPLEMENTED(); >> +#endif >> } >> >> >> uint16_t Simulator::ReadHU(int32_t addr, Instr* instr) { >> +#if V8_TARGET_CAN_READ_UNALIGNED >> + uint16_t* ptr = reinterpret_cast<uint16_t*>(addr); >> + return *ptr; >> +#else >> if ((addr & 1) == 0) { >> uint16_t* ptr = reinterpret_cast<uint16_t*>(addr); >> return *ptr; >> @@ -903,10 +923,15 @@ >> PrintF("Unaligned unsigned halfword read at 0x%08x, pc=%p\n", addr, >> instr); >> UNIMPLEMENTED(); >> return 0; >> +#endif >> } >> >> >> int16_t Simulator::ReadH(int32_t addr, Instr* instr) { >> +#if V8_TARGET_CAN_READ_UNALIGNED >> + int16_t* ptr = reinterpret_cast<int16_t*>(addr); >> + return *ptr; >> +#else >> if ((addr & 1) == 0) { >> int16_t* ptr = reinterpret_cast<int16_t*>(addr); >> return *ptr; >> @@ -914,10 +939,16 @@ >> PrintF("Unaligned signed halfword read at 0x%08x\n", addr); >> UNIMPLEMENTED(); >> return 0; >> +#endif >> } >> >> >> void Simulator::WriteH(int32_t addr, uint16_t value, Instr* instr) { >> +#if V8_TARGET_CAN_READ_UNALIGNED >> + uint16_t* ptr = reinterpret_cast<uint16_t*>(addr); >> + *ptr = value; >> + return; >> +#else >> if ((addr & 1) == 0) { >> uint16_t* ptr = reinterpret_cast<uint16_t*>(addr); >> *ptr = value; >> @@ -925,10 +956,16 @@ >> } >> PrintF("Unaligned unsigned halfword write at 0x%08x, pc=%p\n", addr, >> instr); >> UNIMPLEMENTED(); >> +#endif >> } >> >> >> void Simulator::WriteH(int32_t addr, int16_t value, Instr* instr) { >> +#if V8_TARGET_CAN_READ_UNALIGNED >> + int16_t* ptr = reinterpret_cast<int16_t*>(addr); >> + *ptr = value; >> + return; >> +#else >> if ((addr & 1) == 0) { >> int16_t* ptr = reinterpret_cast<int16_t*>(addr); >> *ptr = value; >> @@ -936,6 +973,7 @@ >> } >> PrintF("Unaligned halfword write at 0x%08x, pc=%p\n", addr, instr); >> UNIMPLEMENTED(); >> +#endif >> } >> >> >> ======================================= >> --- /branches/bleeding_edge/src/globals.h Mon Apr 26 03:59:14 2010 >> +++ /branches/bleeding_edge/src/globals.h Thu May 6 05:49:12 2010 >> @@ -46,6 +46,12 @@ >> #elif defined(__ARMEL__) >> #define V8_HOST_ARCH_ARM 1 >> #define V8_HOST_ARCH_32_BIT 1 >> +// Some CPU-OS combinations allow unaligned access on ARM. We assume >> +// that unaligned accesses are not allowed unless the build system >> +// defines the CAN_USE_UNALIGNED_ACCESSES macro to be non-zero. >> +#if CAN_USE_UNALIGNED_ACCESSES >> +#define V8_HOST_CAN_READ_UNALIGNED 1 >> +#endif >> #elif defined(_MIPS_ARCH_MIPS32R2) >> #define V8_HOST_ARCH_MIPS 1 >> #define V8_HOST_ARCH_32_BIT 1 >> @@ -73,6 +79,12 @@ >> #if defined(V8_TARGET_ARCH_X64) || defined(V8_TARGET_ARCH_IA32) >> #define V8_TARGET_CAN_READ_UNALIGNED 1 >> #elif V8_TARGET_ARCH_ARM >> +// Some CPU-OS combinations allow unaligned access on ARM. We assume >> +// that unaligned accesses are not allowed unless the build system >> +// defines the CAN_USE_UNALIGNED_ACCESSES macro to be non-zero. >> +#if CAN_USE_UNALIGNED_ACCESSES >> +#define V8_TARGET_CAN_READ_UNALIGNED 1 >> +#endif >> #elif V8_TARGET_ARCH_MIPS >> #else >> #error Target architecture is not supported by v8 >> >> -- >> v8-dev mailing list >> [email protected] >> http://groups.google.com/group/v8-dev >> > > -- v8-dev mailing list [email protected] http://groups.google.com/group/v8-dev
