On Mar 3, 2010, at 10:27 AM, Jeff Walther wrote:
I don't understand why 1M X 4 chips would have a different row/column structure than 1M X 1 chips though, unless that's just the way things happened. The article seems to imply that 1M X 1 chips are 9row/11col address bits which 1M X 4 chips are 10row/10col.
The chip topology is four banks which are operated simultaneously, with I/O 0 through 3 active at the same time.
Still, these are row address with *RAS active and column address with *CAS active, and data valid on the rise of *CAS.
*RAS refresh uses more power than the method which Apple selected for these models, but they got bit in the a$$ when the new chips which disallow *CAS refresh.
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