On Mar 4, 2:18 am, yuhong <[email protected]> wrote:
> On Mar 3, 12:08 am, yuhong <[email protected]> wrote:
>
> > If you are wondering why did the Mac II(x) require PAL SIMMs for 4MB
> > and higher, answers are in the end of this 
> > technote:http://web.archive.org/web/20040803140105/http://developer.apple.com/...
> > You will see that it is more correctly 4 Mbits and higher SIMMs, as
> > well as other details.
>
> BTW, I wonder if anyone has managed to hack a PAL into an ordinary
> SIMM using the info provided here?
> The hard part is going to be probably programming it.

To hack a PAL or PLD into an ordinary SIMM you'd have to cut the WE_
lines and reroute them through the PLD and at least tap into the CAS_
and RAS_ lines although there'd probably be no need to cut them.  If
you're able to cut WE_ right at the SIMM pin that's not too bad.
There's only one (pin 21) at the SIMM, although it must fan out to
eight, to supply each chip on the SIMM.

Then I think you'd need a little state machine in the PLD.   Something
like, WE_OUT is high unless WE_IN is low AND CAS_ was low more
recently (or currently) than RAS_.   Depending on the timing of the
memory operations you might be able to do this with a few SOT-23 logic
gates.   Let's see...WE_ can't be low when both RAS_ and CAS_ are
low.  And WE_ should only be low when CAS_ is low, although this
latter condition may be wrong.   I'd need to look at the memory
datasheet, but I think CAS_ is held low along with WE_ while the
column address is supplied, right?  Wrong?

So:

RAS     CAS     WE   |   WE_OUT
   0          0         0     |         1
   0          0         1     |         1
   0          1         0     |         1
   0          1         1     |         1
   1          0         0     |         0
   1          0         1     |         1
   1          1         0     |         1
   1          1         1     |         1

And WE_OUT = RAS' OR CAS OR WE_IN

So if WE_ doesn't need to be held low longer than CAS_ it looks like
one could do it with an inverter and two OR gates or  an inverter and
one three input OR gate.

Jeff Walther

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