From: John Niven <[EMAIL PROTECTED]>
Subject: Re: Macintosh IIfx SIMMs/Information
Date: Wed, 31 Aug 2005 14:27:17 -0700
On Aug 31, 2005, at 11:44 AM, Jeff Walther wrote:
The pinout shows a separate data_in and data_out pin for each bit of
the SIMM. In other words, it's an eight bit SIMM, but instead of
simply having eight data pins Data[0:7] it has eight Data_In[0:7] and
eight Data_Out[0:7] pins.
The "by one bit" DRAMs had separate input and output pins. Most users
just tied them together and hooked them to a bi-directional bus. I
haven't looked into this, but I always assumed that what the IIfx did
was keep the In and Out busses separate so that the timing operations
could be overlapped thus speeding up memory operations.
First, thank you, John for that insightful information. That makes
a lot of sense. Second:
Argghhh! I checked some X 1 DRAM chip datasheets, and shore 'nuff
they have separate data in and data out pins. By 4s and by 8s do
not. This does still leave open the question of whether the IIfx
timing requires the separate data paths. I can probably learn a
little by examining the timing dia grams for the X 1 chips to see if
the output from a read is held while the RAS signal comes in for a
Write.
However, thinking about it now, I'm not sure that makes much sense
really. The data for a write doesn't need to go on the data bus
until shortly before the CAS goes active. So even without separate
data paths, there's most of the RAS operation available for overlap.
And this would only come into play when a write follows a read or
vice versa. This is the kind of thing that would probably be
answered by the IIFX Developer Notes, which I really wish I had a
copy of.
I suppose it is possible that the IIfx puts the data on the bus for a
Write at the same time as RAS goes active. That wouldn't help
performance, but it might have made the IIfx design easier. I really
wish I had that developer note.
Date: Wed, 31 Aug 2005 16:39:42 -0500
From: <[EMAIL PROTECTED]>
Didn't IIfx RAM's have nine bits for error detection? I seem to remember
that there was something different about them and the RAM for a IIfx was
unique to that Mac. All other Macs of that vintage had interchangeable
RAM.
"The Guide to the Macintosh Family Hardware" indicates that both the
IIci and the IIfx had parity options available. These were options
that had to be ordered from the factory as they involved soldering
down extra chips. I know that the IIci has a position on the
motherboard for the parity supporting chip. I've never looked over a
IIfx board to see if it has a similar provision.
The unique thing about the IIfx RAM is that it is on 64 pin SIMMs
instead of 30 pin SIMMs. Strictly speaking, it's not unique because
one (two?) of Apple's LaserWriters used the same 64 pin RAM.
Anyway, if anyone has that IIfx Apple Hardware Developer Note, I'd
sure like to get a copy.
Jeff
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