# HG changeset patch # User Vignesh Vijayakumar<vign...@multicorewareinc.com> # Date 1511338711 -19800 # Wed Nov 22 13:48:31 2017 +0530 # Node ID 46d14b7e78ad312d458a542a9990bbfef1fb4b99 # Parent 3d6605772d179c329fffc669cbecc64afd8c8dff x86: AVX512 interp_4tap_vert_ss_8xN
i444 Size | AVX2 performance | AVX512 performance ---------------------------------------------- 8x8 | 12.89x | 24.63x 8x16 | 17.60x | 26.94x 8x32 | 18.95x | 26.72x diff -r 3d6605772d17 -r 46d14b7e78ad source/common/x86/asm-primitives.cpp --- a/source/common/x86/asm-primitives.cpp Wed Nov 22 13:34:52 2017 +0530 +++ b/source/common/x86/asm-primitives.cpp Wed Nov 22 13:48:31 2017 +0530 @@ -4824,6 +4824,9 @@ p.chroma[X265_CSP_I420].pu[CHROMA_420_32x24].filter_vpp = PFX(interp_4tap_vert_pp_32x24_avx512); p.chroma[X265_CSP_I420].pu[CHROMA_420_32x32].filter_vpp = PFX(interp_4tap_vert_pp_32x32_avx512); + p.chroma[X265_CSP_I420].pu[CHROMA_420_8x8].filter_vss = PFX(interp_4tap_vert_ss_8x8_avx512); + p.chroma[X265_CSP_I420].pu[CHROMA_420_8x16].filter_vss = PFX(interp_4tap_vert_ss_8x16_avx512); + p.chroma[X265_CSP_I420].pu[CHROMA_420_8x32].filter_vss = PFX(interp_4tap_vert_ss_8x32_avx512); p.chroma[X265_CSP_I420].pu[CHROMA_420_16x4].filter_vss = PFX(interp_4tap_vert_ss_16x4_avx512); p.chroma[X265_CSP_I420].pu[CHROMA_420_16x8].filter_vss = PFX(interp_4tap_vert_ss_16x8_avx512); p.chroma[X265_CSP_I420].pu[CHROMA_420_16x12].filter_vss = PFX(interp_4tap_vert_ss_16x12_avx512); @@ -4844,6 +4847,10 @@ p.chroma[X265_CSP_I422].pu[CHROMA_422_32x48].filter_vpp = PFX(interp_4tap_vert_pp_32x48_avx512); p.chroma[X265_CSP_I422].pu[CHROMA_422_32x64].filter_vpp = PFX(interp_4tap_vert_pp_32x64_avx512); + p.chroma[X265_CSP_I422].pu[CHROMA_422_8x8].filter_vss = PFX(interp_4tap_vert_ss_8x8_avx512); + p.chroma[X265_CSP_I422].pu[CHROMA_422_8x16].filter_vss = PFX(interp_4tap_vert_ss_8x16_avx512); + p.chroma[X265_CSP_I422].pu[CHROMA_422_8x32].filter_vss = PFX(interp_4tap_vert_ss_8x32_avx512); + p.chroma[X265_CSP_I422].pu[CHROMA_422_8x64].filter_vss = PFX(interp_4tap_vert_ss_8x64_avx512); p.chroma[X265_CSP_I422].pu[CHROMA_422_16x8].filter_vss = PFX(interp_4tap_vert_ss_16x8_avx512); p.chroma[X265_CSP_I422].pu[CHROMA_422_16x16].filter_vss = PFX(interp_4tap_vert_ss_16x16_avx512); p.chroma[X265_CSP_I422].pu[CHROMA_422_16x24].filter_vss = PFX(interp_4tap_vert_ss_16x24_avx512); @@ -4868,6 +4875,9 @@ p.chroma[X265_CSP_I444].pu[LUMA_64x32].filter_vpp = PFX(interp_4tap_vert_pp_64x32_avx512); p.chroma[X265_CSP_I444].pu[LUMA_64x16].filter_vpp = PFX(interp_4tap_vert_pp_64x16_avx512); + p.chroma[X265_CSP_I444].pu[LUMA_8x8].filter_vss = PFX(interp_4tap_vert_ss_8x8_avx512); + p.chroma[X265_CSP_I444].pu[LUMA_8x16].filter_vss = PFX(interp_4tap_vert_ss_8x16_avx512); + p.chroma[X265_CSP_I444].pu[LUMA_8x32].filter_vss = PFX(interp_4tap_vert_ss_8x32_avx512); p.chroma[X265_CSP_I444].pu[LUMA_16x4].filter_vss = PFX(interp_4tap_vert_ss_16x4_avx512); p.chroma[X265_CSP_I444].pu[LUMA_16x8].filter_vss = PFX(interp_4tap_vert_ss_16x8_avx512); p.chroma[X265_CSP_I444].pu[LUMA_16x12].filter_vss = PFX(interp_4tap_vert_ss_16x12_avx512); diff -r 3d6605772d17 -r 46d14b7e78ad source/common/x86/ipfilter8.asm --- a/source/common/x86/ipfilter8.asm Wed Nov 22 13:34:52 2017 +0530 +++ b/source/common/x86/ipfilter8.asm Wed Nov 22 13:48:31 2017 +0530 @@ -11148,6 +11148,131 @@ ;------------------------------------------------------------------------------------------------------------- ;avx512 chroma_vss code start ;------------------------------------------------------------------------------------------------------------- +%macro PROCESS_CHROMA_VERT_SS_8x8_AVX512 0 + movu xm1, [r0] + lea r6, [r0 + 2 * r1] + lea r8, [r0 + 4 * r1] + lea r9, [r8 + 2 * r1] + vinserti32x4 m1, [r6], 1 + vinserti32x4 m1, [r8], 2 + vinserti32x4 m1, [r9], 3 + movu xm3, [r0 + r1] + vinserti32x4 m3, [r6 + r1], 1 + vinserti32x4 m3, [r8 + r1], 2 + vinserti32x4 m3, [r9 + r1], 3 + punpcklwd m0, m1, m3 + pmaddwd m0, m8 + punpckhwd m1, m3 + pmaddwd m1, m8 + + movu xm4, [r0 + 2 * r1] + vinserti32x4 m4, [r6 + 2 * r1], 1 + vinserti32x4 m4, [r8 + 2 * r1], 2 + vinserti32x4 m4, [r9 + 2 * r1], 3 + punpcklwd m2, m3, m4 + pmaddwd m2, m8 + punpckhwd m3, m4 + pmaddwd m3, m8 + + movu xm5, [r0 + r10] + vinserti32x4 m5, [r6 + r10], 1 + vinserti32x4 m5, [r8 + r10], 2 + vinserti32x4 m5, [r9 + r10], 3 + punpcklwd m6, m4, m5 + pmaddwd m6, m9 + paddd m0, m6 + punpckhwd m4, m5 + pmaddwd m4, m9 + paddd m1, m4 + + movu xm4, [r0 + 4 * r1] + vinserti32x4 m4, [r6 + 4 * r1], 1 + vinserti32x4 m4, [r8 + 4 * r1], 2 + vinserti32x4 m4, [r9 + 4 * r1], 3 + punpcklwd m6, m5, m4 + pmaddwd m6, m9 + paddd m2, m6 + punpckhwd m5, m4 + pmaddwd m5, m9 + paddd m3, m5 + + psrad m0, 6 + psrad m1, 6 + psrad m2, 6 + psrad m3, 6 + packssdw m0, m1 + packssdw m2, m3 + + movu [r2], xm0 + movu [r2 + r3], xm2 + vextracti32x4 [r2 + 2 * r3], m0, 1 + vextracti32x4 [r2 + r7], m2, 1 + lea r2, [r2 + 4 * r3] + vextracti32x4 [r2], m0, 2 + vextracti32x4 [r2 + r3], m2, 2 + vextracti32x4 [r2 + 2 * r3], m0, 3 + vextracti32x4 [r2 + r7], m2, 3 +%endmacro + +;----------------------------------------------------------------------------------------------------------------- +; void interp_4tap_vert(int16_t *src, intptr_t srcStride, int16_t *dst, intptr_t dstStride, int coeffIdx) +;----------------------------------------------------------------------------------------------------------------- +%if ARCH_X86_64 +INIT_ZMM avx512 +cglobal interp_4tap_vert_ss_8x8, 5, 11, 10 + add r1d, r1d + add r3d, r3d + sub r0, r1 + shl r4d, 7 +%ifdef PIC + lea r5, [pw_ChromaCoeffVer_32_avx512] + mova m8, [r5 + r4] + mova m9, [r5 + r4 + mmsize] +%else + lea r5, [pw_ChromaCoeffVer_32_avx512 + r4] + mova m8, [r5] + mova m9, [r5 + mmsize] +%endif + lea r10, [3 * r1] + lea r7, [3 * r3] + PROCESS_CHROMA_VERT_SS_8x8_AVX512 + RET +%endif + +%macro FILTER_VER_SS_CHROMA_8xN_AVX512 1 +INIT_ZMM avx512 +cglobal interp_4tap_vert_ss_8x%1, 5, 11, 10 + add r1d, r1d + add r3d, r3d + sub r0, r1 + shl r4d, 7 +%ifdef PIC + lea r5, [pw_ChromaCoeffVer_32_avx512] + mova m8, [r5 + r4] + mova m9, [r5 + r4 + mmsize] +%else + lea r5, [pw_ChromaCoeffVer_32_avx512 + r4] + mova m8, [r5] + mova m9, [r5 + mmsize] +%endif + lea r10, [3 * r1] + lea r7, [3 * r3] + +%rep %1/8 - 1 + PROCESS_CHROMA_VERT_SS_8x8_AVX512 + lea r0, [r8 + 4 * r1] + lea r2, [r2 + 4 * r3] +%endrep + PROCESS_CHROMA_VERT_SS_8x8_AVX512 + RET +%endmacro + +%if ARCH_X86_64 + FILTER_VER_SS_CHROMA_8xN_AVX512 16 + FILTER_VER_SS_CHROMA_8xN_AVX512 32 + FILTER_VER_SS_CHROMA_8xN_AVX512 64 +%endif + %macro PROCESS_CHROMA_VERT_SS_16x4_AVX512 0 movu ym1, [r0] lea r6, [r0 + 2 * r1] _______________________________________________ x265-devel mailing list x265-devel@videolan.org https://mailman.videolan.org/listinfo/x265-devel