# HG changeset patch # User Vignesh Vijayakumar<vign...@multicorewareinc.com> # Date 1511776446 -19800 # Mon Nov 27 15:24:06 2017 +0530 # Node ID 10ab896094d6e96495e76dfd24c46886cc49c3f4 # Parent 06cc7db3bf0d1a6afb98bb797d70d35ebea5fe32 x86: AVX512 interp_8tap_vert_ss_16xN
Size | AVX2 performance | AVX512 performance ---------------------------------------------- 16x4 | 7.90x | 15.87x 16x8 | 8.58x | 15.10x 16x12 | 10.78x | 15.38x 16x16 | 11.51x | 16.27x 16x32 | 11.92x | 16.93x 16x64 | 10.17x | 17.24x diff -r 06cc7db3bf0d -r 10ab896094d6 source/common/x86/asm-primitives.cpp --- a/source/common/x86/asm-primitives.cpp Mon Nov 27 15:14:35 2017 +0530 +++ b/source/common/x86/asm-primitives.cpp Mon Nov 27 15:24:06 2017 +0530 @@ -4962,6 +4962,12 @@ p.chroma[X265_CSP_I444].pu[LUMA_64x16].filter_vss = PFX(interp_4tap_vert_ss_64x16_avx512); p.chroma[X265_CSP_I444].pu[LUMA_48x64].filter_vss = PFX(interp_4tap_vert_ss_48x64_avx512); + p.pu[LUMA_16x4].luma_vss = PFX(interp_8tap_vert_ss_16x4_avx512); + p.pu[LUMA_16x8].luma_vss = PFX(interp_8tap_vert_ss_16x8_avx512); + p.pu[LUMA_16x12].luma_vss = PFX(interp_8tap_vert_ss_16x12_avx512); + p.pu[LUMA_16x16].luma_vss = PFX(interp_8tap_vert_ss_16x16_avx512); + p.pu[LUMA_16x32].luma_vss = PFX(interp_8tap_vert_ss_16x32_avx512); + p.pu[LUMA_16x64].luma_vss = PFX(interp_8tap_vert_ss_16x64_avx512); p.pu[LUMA_32x64].luma_vss = PFX(interp_8tap_vert_ss_32x64_avx512); p.pu[LUMA_32x32].luma_vss = PFX(interp_8tap_vert_ss_32x32_avx512); p.pu[LUMA_32x24].luma_vss = PFX(interp_8tap_vert_ss_32x24_avx512); diff -r 06cc7db3bf0d -r 10ab896094d6 source/common/x86/ipfilter8.asm --- a/source/common/x86/ipfilter8.asm Mon Nov 27 15:14:35 2017 +0530 +++ b/source/common/x86/ipfilter8.asm Mon Nov 27 15:24:06 2017 +0530 @@ -12811,6 +12811,140 @@ ;------------------------------------------------------------------------------------------------------------- ;avx512 luma_vss code start ;------------------------------------------------------------------------------------------------------------- +%macro PROCESS_LUMA_VERT_SS_16x4_AVX512 0 + movu ym1, [r0] + movu ym3, [r0 + r1] + vinserti32x8 m1, [r0 + 2 * r1], 1 + vinserti32x8 m3, [r0 + r7], 1 + punpcklwd m0, m1, m3 + pmaddwd m0, m15 + punpckhwd m1, m3 + pmaddwd m1, m15 + + lea r6, [r0 + 4 * r1] + movu ym4, [r0 + 2 * r1] + vinserti32x8 m4, [r6], 1 + punpcklwd m2, m3, m4 + pmaddwd m2, m15 + punpckhwd m3, m4 + pmaddwd m3, m15 + + movu ym5, [r0 + r7] + vinserti32x8 m5, [r6 + r1], 1 + punpcklwd m6, m4, m5 + pmaddwd m6, m16 + punpckhwd m4, m5 + pmaddwd m4, m16 + + paddd m0, m6 + paddd m1, m4 + + movu ym4, [r6] + vinserti32x8 m4, [r6 + 2 * r1], 1 + punpcklwd m6, m5, m4 + pmaddwd m6, m16 + punpckhwd m5, m4 + pmaddwd m5, m16 + + paddd m2, m6 + paddd m3, m5 + + movu ym11, [r6 + r1] + vinserti32x8 m11, [r6 + r7], 1 + punpcklwd m8, m4, m11 + pmaddwd m8, m17 + punpckhwd m4, m11 + pmaddwd m4, m17 + + movu ym12, [r6 + 2 * r1] + vinserti32x8 m12, [r6 + 4 * r1], 1 + punpcklwd m10, m11, m12 + pmaddwd m10, m17 + punpckhwd m11, m12 + pmaddwd m11, m17 + + lea r4, [r6 + 4 * r1] + movu ym13, [r6 + r7] + vinserti32x8 m13, [r4 + r1], 1 + punpcklwd m14, m12, m13 + pmaddwd m14, m18 + punpckhwd m12, m13 + pmaddwd m12, m18 + + paddd m8, m14 + paddd m4, m12 + paddd m0, m8 + paddd m1, m4 + + movu ym12, [r6 + 4 * r1] + vinserti32x8 m12, [r4 + 2 * r1], 1 + punpcklwd m14, m13, m12 + pmaddwd m14, m18 + punpckhwd m13, m12 + pmaddwd m13, m18 + + paddd m10, m14 + paddd m11, m13 + paddd m2, m10 + paddd m3, m11 + + psrad m0, 6 + psrad m1, 6 + psrad m2, 6 + psrad m3, 6 + + packssdw m0, m1 + packssdw m2, m3 + + movu [r2], ym0 + movu [r2 + r3], ym2 + vextracti32x8 [r2 + 2 * r3], m0, 1 + vextracti32x8 [r2 + r5], m2, 1 +%endmacro +;----------------------------------------------------------------------------------------------------------------- +; void interp_8tap_vert(int16_t *src, intptr_t srcStride, int16_t *dst, intptr_t dstStride, int coeffIdx) +;----------------------------------------------------------------------------------------------------------------- +%macro FILTER_VER_SS_LUMA_16xN_AVX512 1 +INIT_ZMM avx512 +cglobal interp_8tap_vert_ss_16x%1, 5, 8, 19 + add r1d, r1d + add r3d, r3d + lea r7, [3 * r1] + sub r0, r7 + shl r4d, 8 +%ifdef PIC + lea r5, [pw_LumaCoeffVer_avx512] + mova m15, [r5 + r4] + mova m16, [r5 + r4 + 1 * mmsize] + mova m17, [r5 + r4 + 2 * mmsize] + mova m18, [r5 + r4 + 3 * mmsize] +%else + lea r5, [pw_LumaCoeffVer_avx512 + r4] + mova m15, [r5] + mova m16, [r5 + 1 * mmsize] + mova m17, [r5 + 2 * mmsize] + mova m18, [r5 + 3 * mmsize] +%endif + + lea r5, [3 * r3] +%rep %1/4 - 1 + PROCESS_LUMA_VERT_SS_16x4_AVX512 + lea r0, [r0 + 4 * r1] + lea r2, [r2 + 4 * r3] +%endrep + PROCESS_LUMA_VERT_SS_16x4_AVX512 + RET +%endmacro + +%if ARCH_X86_64 + FILTER_VER_SS_LUMA_16xN_AVX512 4 + FILTER_VER_SS_LUMA_16xN_AVX512 8 + FILTER_VER_SS_LUMA_16xN_AVX512 12 + FILTER_VER_SS_LUMA_16xN_AVX512 16 + FILTER_VER_SS_LUMA_16xN_AVX512 32 + FILTER_VER_SS_LUMA_16xN_AVX512 64 +%endif + %macro PROCESS_LUMA_VERT_SS_32x2_AVX512 0 movu m1, [r0] ;0 row movu m3, [r0 + r1] ;1 row _______________________________________________ x265-devel mailing list x265-devel@videolan.org https://mailman.videolan.org/listinfo/x265-devel