A couple of AMD VPMU fixes
* Handle original (pre-family 15h) MSR range reserved for PMU use
* Stop reporting error back to the guest when reserved PMU MSR bits are
modified since apparently guests (Linux at least) may assume those bits
to be zero. Just make sure those bits are set/cleared prior to being
written according to values discovered during initialization.
Boris Ostrovsky (2):
AMD/VPMU: 0xc0010000 - 0xc001007 MSRs are in PMU range
AMD/VPMU: Keep reserved MSR bits untouched but allow the rest to be
written
xen/arch/x86/cpu/vpmu_amd.c | 16 ++++------------
xen/arch/x86/traps.c | 2 ++
2 files changed, 6 insertions(+), 12 deletions(-)
--
1.8.3.1
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