On 12/15/2012 03:42 PM, GUGLIELMO NAVARRA wrote:
> Reply for FCSE: Omap L138 is based on ARM926ejs (FCSE supported)
> Reply for tsc_info hardcode: The DAVINCI_TIMER0_BASE macro represents
> the physical address of the timer 0 (corrected), which is 64bit timer
> that i use (unchained mode) 32bit for clockevent (BOTTOM) and 32bit
> for clocksource (TOP) . Instead "t->base" represents the virtual
> address obtained from ioremap.
The Xenomai mailing list is an old style mailing list where we do not
top-post. So, please stop top-posting.
If the virtual address of the hardware counter is t->base + t->tim_off
and
t->base is the ioremap of DAVICIN_TIMER0_BASE then the counter physical
address is:
DAVINCI_TIMER0_BASE + t->tim_off
Hence my first question (which you did not answer):
"what about t->tim_off ?"
What I said was if other SOCs or other boards use different timer
configuration where t->base is not DAVINCI_TIMER0_BASE, then you should
not hardcode DAVINCI_TIMER0_BASE in the tsc physical address, yes this
will work in your case, but not for other possible configurations.
--
Gilles.
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